{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,9]],"date-time":"2025-12-09T16:37:32Z","timestamp":1765298252286,"version":"3.46.0"},"publisher-location":"New York, NY, USA","reference-count":23,"publisher":"ACM","funder":[{"DOI":"10.13039\/501100001659","name":"Deutsche Forschungsgemeinschaft","doi-asserted-by":"publisher","award":["528378584"],"award-info":[{"award-number":["528378584"]}],"id":[{"id":"10.13039\/501100001659","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2025,9,28]]},"DOI":"10.1145\/3742872.3758333","type":"proceedings-article","created":{"date-parts":[[2025,12,9]],"date-time":"2025-12-09T16:33:47Z","timestamp":1765298027000},"page":"31-32","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Tutorial: Hardware-Aware Compilation and Simulation for In-Memory Computing"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-5130-9855","authenticated-orcid":false,"given":"Asif Ali","family":"Khan","sequence":"first","affiliation":[{"name":"TU Dresden, Dresden, Germany"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5259-0749","authenticated-orcid":false,"given":"Hadjer","family":"Benmeziane","sequence":"additional","affiliation":[{"name":"IBM, Zurich, Switzerland"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1780-6217","authenticated-orcid":false,"given":"Hamid","family":"Farzaneh","sequence":"additional","affiliation":[{"name":"TU Dresden, Dresden, Germany"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9295-3519","authenticated-orcid":false,"given":"Joao","family":"Lima","sequence":"additional","affiliation":[{"name":"TU Dresden, Dresden, Germany"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7357-7204","authenticated-orcid":false,"given":"William","family":"Simon","sequence":"additional","affiliation":[{"name":"IBM, Zurich, Switzerland"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6788-9823","authenticated-orcid":false,"given":"Yiyu","family":"Shi","sequence":"additional","affiliation":[{"name":"University of Notre Dame, Notre Dame, Indiana, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1830-606X","authenticated-orcid":false,"given":"Zheyu","family":"Yan","sequence":"additional","affiliation":[{"name":"Zhejiang University, Zhejiang, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5603-5243","authenticated-orcid":false,"given":"Abu","family":"Sebastian","sequence":"additional","affiliation":[{"name":"IBM, Zurich, Switzerland"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6636-9738","authenticated-orcid":false,"given":"X. Sharon","family":"Hu","sequence":"additional","affiliation":[{"name":"University of Notre Dame, Notre Dame, Indiana, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5007-445X","authenticated-orcid":false,"given":"Jeronimo","family":"Castrillon","sequence":"additional","affiliation":[{"name":"TU Dresden, Dresden, Germany"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5564-1356","authenticated-orcid":false,"given":"Corey","family":"Lammie","sequence":"additional","affiliation":[{"name":"IBM, Zurich, Switzerland"}]}],"member":"320","published-online":{"date-parts":[[2025,12,9]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"The landscape of compute-near-memory and compute-in-memory: A research and commercial overview,\" arXiv:2401.14428","author":"Khan A. A.","year":"2024","unstructured":"A. A. Khan et al., \"The landscape of compute-near-memory and compute-in-memory: A research and commercial overview,\" arXiv:2401.14428, 2024."},{"key":"e_1_3_2_1_2_1","volume-title":"All-in-memory stochastic computing using reram,\" arXiv preprint arXiv:2504.08340","author":"de Lima J. P. C.","year":"2025","unstructured":"J. P. C. de Lima et al., \"All-in-memory stochastic computing using reram,\" arXiv preprint arXiv:2504.08340, 2025."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1038\/s41467-023-40770-4"},{"key":"e_1_3_2_1_4_1","volume-title":"Mar.","author":"Khan A. A.","year":"2025","unstructured":"A. A. Khan et al., \"Cinm (cinnamon): A compilation infrastructure for heterogeneous compute in-memory and compute near-memory paradigms,\" in Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'25), Mar. 2025."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1038\/s44287-025-00187-1"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2025.3546128"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/3649329.3658485"},{"key":"e_1_3_2_1_8_1","volume-title":"Achieving software-equivalent accuracy for hyperdimensional computing with ferroelectric-based in-memory computing,\" Scientific Reports","author":"Kazemi A.","unstructured":"A. Kazemi et al., \"Achieving software-equivalent accuracy for hyperdimensional computing with ferroelectric-based in-memory computing,\" Scientific Reports, vol. 12, no. 1, 2022."},{"key":"e_1_3_2_1_9_1","volume-title":"Improving realistic worst-case performance of nvcim dnn accelerators through training with right-censored gaussian noise,\" in 2023 IEEE\/ACM International Conference on Computer Aided Design (ICCAD)","author":"Yan Z.","year":"2023","unstructured":"Z. Yan et al., \"Improving realistic worst-case performance of nvcim dnn accelerators through training with right-censored gaussian noise,\" in 2023 IEEE\/ACM International Conference on Computer Aided Design (ICCAD), 2023."},{"key":"e_1_3_2_1_10_1","first-page":"1502","volume-title":"Automation & Test in Europe Conference & Exhibition (DATE). IEEE","author":"J. P.","year":"2022","unstructured":"J. P. C. de Lima and L. Carro, \"Quantization-aware in-situ training for reliable and accurate edge ai,\" in 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2022, pp. 1497\u20131502."},{"key":"e_1_3_2_1_11_1","volume-title":"Fast and robust analog in-memory deep neural network training,\" Nature Communications","author":"Rasch M. J.","unstructured":"M. J. Rasch et al., \"Fast and robust analog in-memory deep neural network training,\" Nature Communications, vol. 15, no. 1, 2024."},{"key":"e_1_3_2_1_12_1","volume-title":"Symp. on Circuits and Systems","author":"Lammie C.","year":"2024","unstructured":"C. Lammie et al., \"Improving the accuracy of analog-based in-memory computing accelerators post-training,\" in IEEE Int. Symp. on Circuits and Systems, 2024."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.array.2021.100116"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1063\/5.0168089"},{"key":"e_1_3_2_1_15_1","volume-title":"A precision-optimized fixed-point near-memory digital processing unit for analog in-memory computing,\" in 2024 IEEE International Symposium on Circuits and Systems (ISCAS)","author":"Ferro E.","year":"2024","unstructured":"E. Ferro et al., \"A precision-optimized fixed-point near-memory digital processing unit for analog in-memory computing,\" in 2024 IEEE International Symposium on Circuits and Systems (ISCAS), 2024."},{"key":"e_1_3_2_1_16_1","volume-title":"Heterogeneous embedded neural processing units utilizing pcm-based analog in-memory computing,\" in IEDM","author":"Boybat I.","year":"2024","unstructured":"I. Boybat et al., \"Heterogeneous embedded neural processing units utilizing pcm-based analog in-memory computing,\" in IEDM, 2024."},{"key":"e_1_3_2_1_17_1","first-page":"630","volume-title":"Harmonica: Hybrid accelerator to overcome imperfections of mixed-signal dnn accelerators,\" in 2024 IEEE International Parallel and Distributed Processing Symposium (IPDPS)","author":"Behnam P.","year":"2024","unstructured":"P. Behnam et al., \"Harmonica: Hybrid accelerator to overcome imperfections of mixed-signal dnn accelerators,\" in 2024 IEEE International Parallel and Distributed Processing Symposium (IPDPS), 2024, pp. 619\u2013630."},{"key":"e_1_3_2_1_18_1","volume-title":"Precision-aware latency and energy balancing on multi-accelerator platforms for dnn inference,\" in 2023 IEEE\/ACM International Symposium on Low Power Electronics and Design (ISLPED)","author":"Risso M.","year":"2023","unstructured":"M. Risso et al., \"Precision-aware latency and energy balancing on multi-accelerator platforms for dnn inference,\" in 2023 IEEE\/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2023."},{"key":"e_1_3_2_1_19_1","article-title":"Occ: An automated end-to-end machine learning optimizing compiler for computing-in-memory","author":"Siemieniuk A.","year":"2021","unstructured":"A. Siemieniuk et al., \"Occ: An automated end-to-end machine learning optimizing compiler for computing-in-memory,\" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2021.","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"e_1_3_2_1_20_1","volume-title":"Conf. on Architectural Support for Programming Languages and Operating Systems","volume":"3","author":"Farzaneh H.","year":"2024","unstructured":"H. Farzaneh et al., \"C4cam: A compiler for cam-based in-memory accelerators,\" in Proc. of the Int. Conf. on Architectural Support for Programming Languages and Operating Systems, Volume 3, ser. ASPLOS 2024, 2024."},{"key":"e_1_3_2_1_21_1","volume-title":"IEEE","author":"da Silva A. F.","year":"2025","unstructured":"A. F. da Silva et al., \"LearnCNM2Predict: Transfer learning-based performance model for cnm systems,\" in International Conference on Embedded Computer Systems: Architectures Modeling and Simulation (SAMOS). IEEE, Jul. 2025."},{"key":"e_1_3_2_1_22_1","first-page":"5","volume-title":"IEEE","author":"Peng X.","year":"2019","unstructured":"X. Peng et al., \"Dnn+ neurosim: An end-to-end benchmarking framework for compute-in-memory accelerators with versatile device technologies,\" in 2019 IEEE international electron devices meeting (IEDM). IEEE, 2019, pp. 32\u20135."},{"issue":"7","key":"e_1_3_2_1_23_1","first-page":"1985","article-title":"Alpine: Analog in-memory acceleration with tight processor integration for deep learning","volume":"72","author":"Klein J.","year":"2022","unstructured":"J. Klein et al., \"Alpine: Analog in-memory acceleration with tight processor integration for deep learning,\" IEEE Transactions on Computers, vol. 72, no. 7, pp. 1985\u20131998, 2022.","journal-title":"IEEE Transactions on Computers"}],"event":{"name":"CASES '25: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems","location":"Taipei International Convention Center (TICC) Taipei Taiwan","acronym":"CASES '25","sponsor":["SIGDA ACM Special Interest Group on Design Automation","SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing","SIGBED ACM Special Interest Group on Embedded Systems","CEDA","IEEE CAS"]},"container-title":["Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3742872.3758333","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,12,9]],"date-time":"2025-12-09T16:33:50Z","timestamp":1765298030000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3742872.3758333"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,9,28]]},"references-count":23,"alternative-id":["10.1145\/3742872.3758333","10.1145\/3742872"],"URL":"https:\/\/doi.org\/10.1145\/3742872.3758333","relation":{},"subject":[],"published":{"date-parts":[[2025,9,28]]},"assertion":[{"value":"2025-12-09","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}