{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,10]],"date-time":"2026-02-10T12:33:16Z","timestamp":1770726796590,"version":"3.49.0"},"publisher-location":"New York, NY, USA","reference-count":29,"publisher":"ACM","content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2026,2,22]]},"DOI":"10.1145\/3748173.3779199","type":"proceedings-article","created":{"date-parts":[[2026,2,5]],"date-time":"2026-02-05T21:17:35Z","timestamp":1770326255000},"page":"201-211","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["TDM Signal Grouping and Package Pin Assignment for 2.5D Multi-FPGA Systems with Lookahead Placement"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-7054-384X","authenticated-orcid":false,"given":"Jiarui","family":"Wang","sequence":"first","affiliation":[{"name":"School of Computer Science, Peking University, Beijing, Beijing, China and School of Integrated Circuits, Peking University, Beijing, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0003-1135-5667","authenticated-orcid":false,"given":"Runzhe","family":"Tao","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Peking University, Beijing, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3787-1534","authenticated-orcid":false,"given":"Jing","family":"Mai","sequence":"additional","affiliation":[{"name":"School of Computer Science, Peking University, Beijing, Beijing, China and School of Integrated Circuits, Peking University, Beijing, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0006-7958-8485","authenticated-orcid":false,"given":"Xun","family":"Jiang","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Peking University, Beijing, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8138-1911","authenticated-orcid":false,"given":"Shenghua","family":"Wang","sequence":"additional","affiliation":[{"name":"S2C Inc., Shenzhen, Guangdong, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7577-329X","authenticated-orcid":false,"given":"Cuiliu","family":"Yang","sequence":"additional","affiliation":[{"name":"S2C Inc., Shenzhen, Guangdong, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0004-8792-8537","authenticated-orcid":false,"given":"Haoyu","family":"Jie","sequence":"additional","affiliation":[{"name":"S2C Inc., Shenzhen, Guangdong, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0242-0116","authenticated-orcid":false,"given":"Kan","family":"Huang","sequence":"additional","affiliation":[{"name":"S2C Inc., Shenzhen, Guangdong, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0003-3924-2154","authenticated-orcid":false,"given":"Richard Y.","family":"Sun","sequence":"additional","affiliation":[{"name":"S2C Inc., Shenzhen, Guangdong, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0977-2774","authenticated-orcid":false,"given":"Yibo","family":"Lin","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Peking University, Beijing, Beijing, China, Institute of EDA, Peking University, Beijing, Beijing, China, and Advanced Innovation Center for Integrated Circuits, Beijing, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2026,2,21]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"Premium VP1902 Adaptive SoC,'' 2025","year":"1902","unstructured":"AMD, ''Versal Premium VP1902 Adaptive SoC,'' 2025. https:\/\/www.amd.com\/en\/products\/adaptive-socs-and-fpgas\/versal\/premium-series\/vp1902.html."},{"key":"e_1_3_2_1_2_1","volume-title":"Multi-die heterogeneous FPGA's: How balanced should netlist partitioning be?,'' SLIP '22","author":"Raikar R.","year":"2023","unstructured":"R. Raikar and D. Stroobandt, ''Multi-die heterogeneous FPGA's: How balanced should netlist partitioning be?,'' SLIP '22, 2023."},{"key":"e_1_3_2_1_3_1","first-page":"16","volume-title":"Placement strategies for 2.5D FPGA, fabric architectures,'' in 2018 28th International Conference on Field Programmable Logic and Applications (FPL)","author":"Ravishankar C.","year":"2018","unstructured":"C. Ravishankar, D. Gaitonde, and T. Bauer, ''Placement strategies for 2.5D FPGA, fabric architectures,'' in 2018 28th International Conference on Field Programmable Logic and Applications (FPL), pp. 16-164, 2018."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.640619"},{"key":"e_1_3_2_1_5_1","volume-title":"Emulation Systems | System Verification","year":"2024","unstructured":"Synopsys, ''Emulation Systems | System Verification,'' 2024. https:\/\/www.synopsys.com\/verification\/emulation."},{"key":"e_1_3_2_1_6_1","volume-title":"How do logic simulation, emulation, and FPGA prototyping work?","author":"Zhang X.","year":"2023","unstructured":"X. Zhang, ''How do logic simulation, emulation, and FPGA prototyping work?,'' 2023. https:\/\/www.s2cinc.com\/resources\/lit\/en\/wp\/s2c-how-do-logic-simulation-emulation-and-fpga-prototyping-work.pdf."},{"key":"e_1_3_2_1_7_1","first-page":"1","volume-title":"Synergistic die-level router for multi-FPGA system with time-division multiplexing optimization,'' in 2025 62nd ACM\/IEEE Design Automation Conference (DAC)","author":"Wang J.","year":"2025","unstructured":"J. Wang, Y. Liu, and Y. Lin, ''Synergistic die-level router for multi-FPGA system with time-division multiplexing optimization,'' in 2025 62nd ACM\/IEEE Design Automation Conference (DAC), pp. 1-7, 2025."},{"key":"e_1_3_2_1_8_1","first-page":"324","volume-title":"System routing and TDM assignment optimization in multi-2.5D FPGA-based prototyping systems,'' in 2024 2nd International Symposium of Electronics Design Automation (ISEDA)","author":"Huang C.","year":"2024","unstructured":"C. Huang, P. Chu, S. Bi, R. Sun, and H. You, ''System routing and TDM assignment optimization in multi-2.5D FPGA-based prototyping systems,'' in 2024 2nd International Symposium of Electronics Design Automation (ISEDA), pp. 324-331, 2024."},{"key":"e_1_3_2_1_9_1","volume-title":"AMD Vivado Design Suite","author":"AMD","year":"2025","unstructured":"AMD, ''AMD Vivado Design Suite,'' 2025. https:\/\/www.amd.com\/en\/products\/software\/adaptive-socs-and-fpgas\/vivado.html."},{"key":"e_1_3_2_1_10_1","volume-title":"Quartus\u00ae Prime Design Software | Altera\u00ae FPGA","year":"2025","unstructured":"Altrea, ''Quartus\u00ae Prime Design Software | Altera\u00ae FPGA,'' 2025. https:\/\/www.altera.com\/products\/development-tools\/quartus."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.3001392"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"crossref","unstructured":"J. Mai J. Wang Y. Chen Z. Guo X. Jiang Y. Liang and Y. Lin ''OpenPARF 3.0: Robust multi-electrostatics based FPGA macro placement considering cascaded macros groups and fence regions '' in 2024 2nd International Symposium of Electronics Design Automation (ISEDA) pp. 374-379 2024.","DOI":"10.1109\/ISEDA62518.2024.10617535"},{"key":"e_1_3_2_1_13_1","unstructured":"Chips-Alliance ''FPGA-Interchange-Schema '' 2025. https:\/\/github.com\/chipsalliance\/fpga-interchange-schema."},{"key":"e_1_3_2_1_14_1","first-page":"133","volume-title":"RapidWright: Enabling custom crafted implementations for FPGAs,'' in 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)","author":"Lavin C.","year":"2018","unstructured":"C. Lavin and A. Kaviani, ''RapidWright: Enabling custom crafted implementations for FPGAs,'' in 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 133-140, April 2018."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2023.3340554"},{"key":"e_1_3_2_1_16_1","first-page":"300","volume-title":"DREAMPlaceFPGA: An open-source analytical placer for large scale heterogeneous FPGAs using deep-learning toolkit,'' in 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)","author":"Rajarathnam R. S.","year":"2022","unstructured":"R. S. Rajarathnam, M. B. Alawieh, Z. Jiang, M. Iyer, and D. Z. Pan, ''DREAMPlaceFPGA: An open-source analytical placer for large scale heterogeneous FPGAs using deep-learning toolkit,'' in 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 300-306, 2022."},{"key":"e_1_3_2_1_17_1","volume-title":"Virtex UltraScale VU19P FPGAs","author":"AMD","year":"2025","unstructured":"AMD, ''Virtex UltraScale VU19P FPGAs,'' 2025. https:\/\/www.amd.com\/en\/products\/adaptive-socs-and-fpgas\/fpga\/virtex-ultrascale-plus-vu19p.html."},{"key":"e_1_3_2_1_18_1","volume-title":"ACM","author":"Lu J.","year":"2014","unstructured":"J. Lu, P. Chen, C.-C. Chang, L. Sha, D. J.-H. Huang, C.-C. Teng, and C.-K. Cheng, ''ePlace: Electrostatics based placement using Nesterov's method,'' in Proceedings of the 51st Annual Design Automation Conference (DAC) (New York, NY, USA), pp. 1-6, ACM, 2014."},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2859220"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.3003843"},{"key":"e_1_3_2_1_21_1","first-page":"1","volume-title":"elfplace: Electrostatics-based placement for large-scale heterogeneous FPGAs,'' in 2019 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)","author":"Li W.","year":"2019","unstructured":"W. Li, Y. Lin, and D. Z. Pan, ''elfplace: Electrostatics-based placement for large-scale heterogeneous FPGAs,'' in 2019 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), pp. 1-8, 2019."},{"key":"e_1_3_2_1_22_1","first-page":"1","volume-title":"Automation & Test in Europe Conference & Exhibition","author":"Spindler P.","year":"2007","unstructured":"P. Spindler and F. M. Johannes, ''Fast and accurate routing demand estimation for efficient routability-driven placement,'' in 2007 Design, Automation & Test in Europe Conference & Exhibition, pp. 1-6, 2007."},{"key":"e_1_3_2_1_23_1","unstructured":"AMD ''Virtex UltraScale FPGAs '' 2025. https:\/\/www.amd.com\/en\/products\/adaptive-socs-and-fpgas\/fpga\/virtex-ultrascale-plus.html."},{"key":"e_1_3_2_1_24_1","first-page":"1","volume-title":"The 2023 MLCAD FPGA macro placement benchmark design suite and contest results,'' in 2023 ACM\/IEEE 5th Workshop on Machine Learning for CAD (MLCAD)","author":"Bustany I.","year":"2023","unstructured":"I. Bustany, G. Gasparyan, A. Gupta, A. B. Kahng, M. Kalase, W. Li, and B. Pramanik, ''The 2023 MLCAD FPGA macro placement benchmark design suite and contest results,'' in 2023 ACM\/IEEE 5th Workshop on Machine Learning for CAD (MLCAD), pp. 1-6, 2023."},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2023.3313101"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-68279-0_2"},{"key":"e_1_3_2_1_27_1","volume-title":"S2C prototyping: FPGA ASIC SoC IP verification, validation, emulation","year":"2024","unstructured":"S2C, ''S2C prototyping: FPGA ASIC SoC IP verification, validation, emulation,'' 2024. https:\/\/www.s2cinc.com."},{"key":"e_1_3_2_1_28_1","unstructured":"''ISPD16 contest.'' http:\/\/www.ispd.cc\/contests\/16."},{"key":"e_1_3_2_1_29_1","unstructured":"''ISPD17 contest.'' http:\/\/www.ispd.cc\/contests\/17."}],"event":{"name":"FPGA '26:The 2026 ACM\/SIGDA International Symposium on Field Programmable Gate Arrays","location":"Seaside CA USA","sponsor":["SIGDA ACM Special Interest Group on Design Automation"]},"container-title":["Proceedings of the 2026 ACM\/SIGDA International Symposium on Field Programmable Gate Arrays"],"original-title":[],"deposited":{"date-parts":[[2026,2,9]],"date-time":"2026-02-09T16:16:21Z","timestamp":1770653781000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3748173.3779199"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,2,21]]},"references-count":29,"alternative-id":["10.1145\/3748173.3779199","10.1145\/3748173"],"URL":"https:\/\/doi.org\/10.1145\/3748173.3779199","relation":{},"subject":[],"published":{"date-parts":[[2026,2,21]]},"assertion":[{"value":"2026-02-21","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}