{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,10,22]],"date-time":"2026-10-22T17:12:28Z","timestamp":1792689148030,"version":"4.5.0"},"reference-count":49,"publisher":"Association for Computing Machinery (ACM)","issue":"5","funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"crossref","award":["62025404, 92473207, and 62204111"],"award-info":[{"award-number":["62025404, 92473207, and 62204111"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2025,9,30]]},"abstract":"<jats:p>Chiplet technology has been a hot topic due to its potential for more efficient implementation of large-scale integrated circuits. In chiplet manufacturing, the general-purpose active interposer usually integrates chiplets from different vendors with a typical mesh network. This method of manufacturing is broadly recognized for its cost-efficiency. However, untrusted vendors make the chiplet system vulnerable to security threats such as timing side-channel attacks (TSA) based on network contention information. Even worse, the reliability of each chiplet is usually unknown beforehand to a general-purpose interposer\u2019s manufacturer, so that TSAs can be on arbitrary chiplets at arbitrary time in the manufacturer\u2019s view. To address this challenge, this work first quantitatively analyzes the attack patterns including reinforced styles, based on which, a resilient interposer architecture named Resister is proposed. A hardware defender is designed in every router to globally detect the malicious transaction patterns at runtime, and adaptively detour the transaction packets accordingly for security while maintaining the performance. According to the evaluation of GEM5 on SPEC 2017 and PARSEC benchmarks, Resister can effectively mitigate TSA with only a 1.7% performance overhead.<\/jats:p>","DOI":"10.1145\/3748258","type":"journal-article","created":{"date-parts":[[2025,7,9]],"date-time":"2025-07-09T14:56:02Z","timestamp":1752072962000},"page":"1-23","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["Resister: A Resilient Interposer Architecture for Chiplet to Mitigate Timing Side-Channel Attacks"],"prefix":"10.1145","volume":"30","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-0718-1556","authenticated-orcid":false,"given":"Xinrui","family":"Wang","sequence":"first","affiliation":[{"name":"Nanjing University","place":["Nanjing, China"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9943-0550","authenticated-orcid":false,"given":"Lang","family":"Feng","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Sun Yat-Sen University","place":["Shenzhen, China"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0646-4183","authenticated-orcid":false,"given":"Yujie","family":"Wang","sequence":"additional","affiliation":[{"name":"Institute of Computing Technology Chinese Academy of Sciences","place":["Beijing, China"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0006-1394-6526","authenticated-orcid":false,"given":"Taotao","family":"Xu","sequence":"additional","affiliation":[{"name":"Institute of Computing Technology Chinese Academy of Sciences","place":["Beijing, China"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0904-6681","authenticated-orcid":false,"given":"Yinhe","family":"Han","sequence":"additional","affiliation":[{"name":"Institute of Computing Technology Chinese Academy of Sciences","place":["Beijing, China"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7227-4786","authenticated-orcid":false,"given":"Zhongfeng","family":"Wang","sequence":"additional","affiliation":[{"name":"Nanjing University","place":["Nanjing, China"]},{"name":"School of Integrated Circuits, Sun Yat-Sen University","place":["Nanjing, China"]}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2025,8,12]]},"reference":[{"key":"e_1_3_2_2_2","first-page":"256","volume-title":"Topics in Cryptology\u2013CT-RSA","author":"Ac\u0131i\u00e7mez Onur","year":"2008","unstructured":"Onur Ac\u0131i\u00e7mez and Werner Schindler. 2008. A vulnerability in RSA implementations due to instruction cache analysis and its demonstration on OpenSSL. In Topics in Cryptology\u2013CT-RSA. 256\u2013273."},{"key":"e_1_3_2_3_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2009.4919636"},{"key":"e_1_3_2_4_2","doi-asserted-by":"publisher","DOI":"10.1145\/3140659.3080231"},{"key":"e_1_3_2_5_2","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218539"},{"key":"e_1_3_2_6_2","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"e_1_3_2_7_2","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_3_2_8_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2023.3347302"},{"key":"e_1_3_2_9_2","doi-asserted-by":"publisher","DOI":"10.1145\/356586.356588"},{"key":"e_1_3_2_10_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.2970019"},{"key":"e_1_3_2_11_2","unstructured":"2015. Cryptographic Algorithms. Retrieved May 10 2025 from https:\/\/github.com\/JamisHoo\/Cryptographic-Algorithms\/tree\/master\/"},{"key":"e_1_3_2_12_2","first-page":"2857","volume-title":"USENIX Security Symposium (USENIX Security)","author":"Dai Miles","year":"2022","unstructured":"Miles Dai, Riccardo Paccagnella, Miguel Gomez-Garcia, John McCalpin, and Mengjia Yan. 2022. Don\u2019t mesh around: Side-channel attacks and mitigations on mesh interconnects. In USENIX Security Symposium (USENIX Security). 2857\u20132874."},{"key":"e_1_3_2_13_2","doi-asserted-by":"publisher","DOI":"10.1145\/3649329.3657321"},{"key":"e_1_3_2_14_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA52012.2021.00080"},{"key":"e_1_3_2_15_2","unstructured":"2023. Educational ECDSA implementation. Retrieved May 10 2025 from https:\/\/github.com\/sholtrop\/chipwhisperer_lite_ecdsa_vuln\/tree\/master"},{"key":"e_1_3_2_16_2","doi-asserted-by":"publisher","DOI":"10.14778\/3681954.3682011"},{"key":"e_1_3_2_17_2","unstructured":"GNUPG. 2021. Libgcrypt. Retrieved July 15 2024 from https:\/\/gnupg.org\/software\/libgcrypt\/index.html"},{"key":"e_1_3_2_18_2","doi-asserted-by":"publisher","DOI":"10.14722\/ndss.2020.23018"},{"key":"e_1_3_2_19_2","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2015.7231374"},{"key":"e_1_3_2_20_2","doi-asserted-by":"publisher","DOI":"10.1109\/DAC56929.2023.10248006"},{"key":"e_1_3_2_21_2","doi-asserted-by":"publisher","DOI":"10.1109\/DAC56929.2023.10248006"},{"key":"e_1_3_2_22_2","unstructured":"Intel. 2022. Guidelines for mitigating timing side channels against cryptographic implementations. Retrieved from https:\/\/www.intel.com\/content\/www\/us\/en\/developer\/articles\/technical\/software-security-guidance\/secure-coding\/mitigate-timing-side-channel-crypto-implementation.html"},{"issue":"7","key":"e_1_3_2_23_2","first-page":"973","article-title":"Heterogeneous integration for performance and scaling","volume":"6","author":"Iyer Subramanian S.","year":"2016","unstructured":"Subramanian S. Iyer. 2016. Heterogeneous integration for performance and scaling. IEEE Trans. Compon. Packag. Technol. 6, 7 (2016), 973\u2013982.","journal-title":"IEEE Trans. Compon. Packag. Technol."},{"key":"e_1_3_2_24_2","doi-asserted-by":"publisher","DOI":"10.1109\/ETS56758.2023.10174000"},{"key":"e_1_3_2_25_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2024.3419579"},{"key":"e_1_3_2_26_2","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2023.3276709"},{"key":"e_1_3_2_27_2","doi-asserted-by":"publisher","DOI":"10.1109\/3DIC.2015.7334619"},{"key":"e_1_3_2_28_2","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-48405-1_25"},{"key":"e_1_3_2_29_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1981.6312171"},{"key":"e_1_3_2_30_2","doi-asserted-by":"publisher","DOI":"10.1145\/3508352.3549464"},{"key":"e_1_3_2_31_2","unstructured":"Zhuoran Liu Niels Samwel Leo Weissbart Zhengyu Zhao Dirk Lauret Lejla Batina and Martha Larson. 2021. Screen gleaning: A screen reading TEMPEST attack on mobile devices exploiting an electromagnetic side channel. Annual Network and Distributed System Security Symposium (NDSS\u201921)."},{"key":"e_1_3_2_32_2","article-title":"Constant-Time Arithmetic for Safer Cryptography","author":"Meier L\u00fac\u00e1s Cr\u00edost\u00f3ir","year":"2021","unstructured":"L\u00fac\u00e1s Cr\u00edost\u00f3ir Meier, Simone Colombo, Marin Thiercelin, and Bryan Ford. 2021. Constant-Time Arithmetic for Safer Cryptography. Cryptology ePrint Archive, Paper 2021\/1121. Retrieved from https:\/\/eprint.iacr.org\/2021\/1121","journal-title":"Cryptology ePrint Archive, Paper 2021\/1121"},{"key":"e_1_3_2_33_2","first-page":"57","volume-title":"ACM\/IEEE Annual International Symposium on Computer Architecture (ISCA)","author":"Naffziger Samuel","year":"2021","unstructured":"Samuel Naffziger, Noah Beck, Thomas Burd, Kevin Lepak, Gabriel H. Loh, Mahesh Subramony, and Sean White. 2021. Pioneering chiplet technology and design for the AMD EPYC\u2122and ryzen\u2122processor families : Industrial product. In ACM\/IEEE Annual International Symposium on Computer Architecture (ISCA). 57\u201370."},{"key":"e_1_3_2_34_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9063103"},{"key":"e_1_3_2_35_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42614.2022.9731107"},{"key":"e_1_3_2_36_2","first-page":"645","volume-title":"USENIX Security Symposium (USENIX Security)","author":"Paccagnella Riccardo","year":"2021","unstructured":"Riccardo Paccagnella, Licheng Luo, and Christopher W. Fletcher. 2021. Lord of the ring(s): Side channel attacks on the CPU on-chip ring interconnect are practical. In USENIX Security Symposium (USENIX Security). 645\u2013662."},{"key":"e_1_3_2_37_2","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2012.25"},{"key":"e_1_3_2_38_2","doi-asserted-by":"crossref","unstructured":"James Bucek Klaus-Dieter Lange and J\u00f3akim v. Kistowski. 2018. SPEC CPU2017: Next-generation compute benchmark. Companion of ACM\/SPEC International Conference on Performance Engineering. 41\u201342. Retrieved from https:\/\/www.spec.org\/cpu2017\/","DOI":"10.1145\/3185768.3185771"},{"key":"e_1_3_2_39_2","doi-asserted-by":"publisher","DOI":"10.1145\/3649476.3658763"},{"key":"e_1_3_2_40_2","doi-asserted-by":"publisher","DOI":"10.23919\/DATE54114.2022.9774617"},{"key":"e_1_3_2_41_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA52012.2021.00021"},{"key":"e_1_3_2_42_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.42"},{"key":"e_1_3_2_43_2","doi-asserted-by":"publisher","DOI":"10.1109\/SP46214.2022.9833794"},{"key":"e_1_3_2_44_2","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2012.24"},{"key":"e_1_3_2_45_2","doi-asserted-by":"publisher","DOI":"10.1145\/2508148.2485972"},{"key":"e_1_3_2_46_2","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2021.3085578"},{"key":"e_1_3_2_47_2","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2019.00004"},{"key":"e_1_3_2_48_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757434"},{"key":"e_1_3_2_49_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00066"},{"key":"e_1_3_2_50_2","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218654"}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3748258","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,12]],"date-time":"2025-08-12T13:16:20Z","timestamp":1755004580000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3748258"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,8,12]]},"references-count":49,"journal-issue":{"issue":"5","published-print":{"date-parts":[[2025,9,30]]}},"alternative-id":["10.1145\/3748258"],"URL":"https:\/\/doi.org\/10.1145\/3748258","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"value":"1084-4309","type":"print"},{"value":"1557-7309","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,8,12]]},"assertion":[{"value":"2025-03-10","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2025-07-05","order":2,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2025-08-12","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}