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Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2026,7,31]]},"abstract":"<jats:p>Technology mapping involves mapping logical circuits to a library of standard cells. Traditionally, a full technology library is used, leading to a large search space and potential runtime overhead. Motivated by randomly sampled technology mapping case studies, we propose MapTune to address this challenge by utilizing reinforcement learning to make design-specific cell selection choices. By learning from the environment and guided by the reward, MapTune refines the cell selection process, resulting in a reduced search space and potentially improved mapping quality. The effectiveness of MapTune is evaluated on a wide range of benchmarks, different technology libraries, and various technology mappers. The empirical results demonstrate that MapTune achieves higher mapping accuracy and reduces delay\/area across various circuit designs, technology libraries, and mappers. The article also discusses the Pareto-Optimal exploration and confirms the perpetual delay-area tradeoff. Conducted on benchmark suites ISCAS 85\/89, ITC\/ISCAS 99, VTR8.0, and EPFL benchmarks, the post-technology mapping and post-sizing quality-of-results (QoR) have been significantly improved, with average Area-Delay Product (ADP) improvement of 16.56% among all different exploration settings in MapTune. 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