{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,15]],"date-time":"2025-08-15T02:18:57Z","timestamp":1755224337140,"version":"3.43.0"},"reference-count":53,"publisher":"Association for Computing Machinery (ACM)","issue":"5","funder":[{"name":"National Natural Science Foundation of China\u00a0(NSFC) Research","award":["92373207"],"award-info":[{"award-number":["92373207"]}]},{"name":"NSFC Research","award":["62274100"],"award-info":[{"award-number":["62274100"]}]},{"name":"Key Research and Development Program of Ningbo City","award":["2023Z071"],"award-info":[{"award-number":["2023Z071"]}]},{"name":"State Key Laboratory of Integrated Chips and Systems, Fudan University","award":["SKLICS-Z202404"],"award-info":[{"award-number":["SKLICS-Z202404"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2025,9,30]]},"abstract":"<jats:p>\n            Logic synthesis is crucial in digital design automation, significantly enhancing performance, reducing area, and lowering power consumption through technology-independent optimization followed by technology mapping. Logic rewriting, a key strategy for optimization, iteratively replaces portions of logic circuits with more compact implementations. Despite historical advancements, challenges remain in subgraph selection, technology-dependent metrics, and performance-runtime trade-offs. This article presents a novel\n            <jats:underline>Te<\/jats:underline>\n            chnology-\n            <jats:underline>a<\/jats:underline>\n            ware logic\n            <jats:underline>R<\/jats:underline>\n            e\n            <jats:underline>W<\/jats:underline>\n            riting (\n            <jats:monospace>TeaRW<\/jats:monospace>\n            ) framework to address these challenges.\n            <jats:monospace>TeaRW<\/jats:monospace>\n            incorporates a technology-aware rewriting algorithm that evaluates post-mapping netlist metrics during the technology-independent optimization phase. It employs four distinct subgraph rewriting techniques to maximize the effectiveness of local optimization. For efficiency,\n            <jats:monospace>TeaRW<\/jats:monospace>\n            utilizes an optimized logic representation database derived from exact synthesis, enabling cost-effective replacements. Experimental results on real-world benchmarks show improvements over the ABC tool, including an average Area-Delay-Product\u00a0(ADP) improvement of 8.18% in delay-oriented optimization and 0.28% in area-oriented optimization when compared to state-of-the-art optimization scripts.\n          <\/jats:p>","DOI":"10.1145\/3749103","type":"journal-article","created":{"date-parts":[[2025,7,21]],"date-time":"2025-07-21T11:20:07Z","timestamp":1753096807000},"page":"1-29","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Rethinking Logic Rewriting: Technology-Aware Subgraph Matching with Exact Synthesis"],"prefix":"10.1145","volume":"30","author":[{"ORCID":"https:\/\/orcid.org\/0009-0009-0874-4518","authenticated-orcid":false,"given":"Hongyang","family":"Pan","sequence":"first","affiliation":[{"name":"State Key Laboratory of Integrated Chips and Systems, Fudan University","place":["Shanghai, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2698-141X","authenticated-orcid":false,"given":"Keren","family":"Zhu","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Integrated Chips and Systems, Fudan University","place":["Shanghai, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2164-8175","authenticated-orcid":false,"given":"Fan","family":"Yang","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Integrated Chips and Systems, Fudan University","place":["Shanghai, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8097-4053","authenticated-orcid":false,"given":"Xuan","family":"Zeng","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Integrated Chips and Systems, Fudan University","place":["Shanghai, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0005-8059-3444","authenticated-orcid":false,"given":"Sen","family":"Liu","sequence":"additional","affiliation":[{"name":"Giga Design Automation Co., Ltd.","place":["Beijing, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8565-4457","authenticated-orcid":false,"given":"Yong","family":"Xiao","sequence":"additional","affiliation":[{"name":"Giga Design Automation Co., Ltd.","place":["Beijing, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4414-3519","authenticated-orcid":false,"given":"Yun","family":"Shao","sequence":"additional","affiliation":[{"name":"Giga Design Automation Co., Ltd.","place":["Beijing, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5718-4822","authenticated-orcid":false,"given":"Zhufei","family":"Chu","sequence":"additional","affiliation":[{"name":"Ningbo University","place":["Ningbo, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2025,8,12]]},"reference":[{"key":"e_1_3_2_2_2","article-title":"ABC: System for sequential logic synthesis and formal verification","author":"Mishchenko Alan","year":"2024","unstructured":"Alan Mishchenko. 2024. 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