{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,20]],"date-time":"2026-04-20T22:51:20Z","timestamp":1776725480317,"version":"3.51.2"},"reference-count":48,"publisher":"Association for Computing Machinery (ACM)","issue":"3","funder":[{"name":"Advanced Scientific Computing Research (ASCR) program of the Department of Energy","award":["DE-SC0022881"],"award-info":[{"award-number":["DE-SC0022881"]}]},{"name":"National Science Foundation","award":["CCF-2219753"],"award-info":[{"award-number":["CCF-2219753"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2025,7,31]]},"abstract":"<jats:p>Reconfigurable devices are gaining increasing attention as a viable alternative and supplementary solution to the traditional CMOS technology. In this article, we develop a more efficient field-programmable gate array (FPGA) based on the reconfigurable field-effective transistor (RFET). We use the multi-gate characteristics of RFET to redesign the key components of FPGAs, namely SRAM-controlled multiplexer and look-up tables. The compact structure of the proposed design requires fewer transistors and leads to reduced delay of the overall FPGA system. In addition, we develop a comprehensive technology\/system co-design and co-optimization framework to thoroughly investigate the design space, including various device- and system-level design parameters. A series of benchmark tests show that under the optimal design, up to 32% and 13% reduction can be achieved in delay and energy-delay product (EDP), respectively, compared to the traditional CMOS FPGAs.<\/jats:p>","DOI":"10.1145\/3750730","type":"journal-article","created":{"date-parts":[[2025,7,25]],"date-time":"2025-07-25T06:40:47Z","timestamp":1753425647000},"page":"1-21","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Technology\/System Co-Optimization for FPGA Using Emerging Reconfigurable Logic Device"],"prefix":"10.1145","volume":"21","author":[{"ORCID":"https:\/\/orcid.org\/0009-0001-2570-0690","authenticated-orcid":false,"given":"Sheng","family":"Lu","sequence":"first","affiliation":[{"name":"Department of Electrical Engineering, The University of Texas at Arlington, Arlington, Texas, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8149-8696","authenticated-orcid":false,"given":"Liuting","family":"Shang","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, The University of Texas at Arlington, Arlington, Texas, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0749-0394","authenticated-orcid":false,"given":"Sungyong","family":"Jung","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering and Computer Science, South Dakota State University, Brookings, South Dakota, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6925-0775","authenticated-orcid":false,"given":"Yichen","family":"Zhang","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, The University of Texas at Arlington, Arlington, Texas, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3630-8010","authenticated-orcid":false,"given":"Qilian","family":"Liang","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, The University of Texas at Arlington, Arlington, Texas, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9161-1728","authenticated-orcid":false,"given":"Chenyun","family":"Pan","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, The University of Texas at Arlington, Arlington, Texas, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2025,9,11]]},"reference":[{"key":"e_1_3_1_2_2","doi-asserted-by":"publisher","DOI":"10.1145\/329166.329171"},{"key":"e_1_3_1_3_2","unstructured":"V. Betz J. Rose and A. Marquardt. 2012. Architecture and CAD for Deep-Submicron FPGAs. Springer Science & Business Media."},{"key":"e_1_3_1_4_2","doi-asserted-by":"publisher","DOI":"10.1145\/1117201.1117219"},{"key":"e_1_3_1_5_2","doi-asserted-by":"crossref","first-page":"269","DOI":"10.1109\/FPT.2007.4439263","volume-title":"Proceedings of the 2007 International Conference on Field-Programmable Technology","author":"Marrakchi Z.","year":"2007","unstructured":"Z. Marrakchi, H. Mrabet, C. Masson, and H. Mehrez. 2007. Efficient mesh of tree interconnect for FPGA architecture. In Proceedings of the 2007 International Conference on Field-Programmable Technology. IEEE, 269\u2013272."},{"key":"e_1_3_1_6_2","first-page":"1","volume-title":"Proceedings of the 2014 International 3D Systems Integration Conference (3DIC)","author":"Chtourou S.","year":"2014","unstructured":"S. Chtourou, M. Abid, V. Pangracious, E. Amouri, Z. Marrakchi, and H. Mehrez. 2014. Three-dimensional mesh of clusters: An alternative unified high performance interconnect architecture for 3D-FPGA implementation. In Proceedings of the 2014 International 3D Systems Integration Conference (3DIC). IEEE, 1\u20137."},{"key":"e_1_3_1_7_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2016.2636141"},{"key":"e_1_3_1_8_2","doi-asserted-by":"publisher","DOI":"10.1021\/nl203094h"},{"key":"e_1_3_1_9_2","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2015.2429893"},{"key":"e_1_3_1_10_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2020.3035889"},{"key":"e_1_3_1_11_2","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2022.3216969"},{"key":"e_1_3_1_12_2","first-page":"728","article-title":"Germanium nanowire reconfigurable transistor model for predictive technology evaluation","volume":"21","author":"Quijada J. N.","year":"2022","unstructured":"J. N. Quijada, T. Baldauf, S. Rai, A. Heinzig, A. Kumar, W. M. Weber, T. Mikolajick, and J. Trommer. 2022. Germanium nanowire reconfigurable transistor model for predictive technology evaluation. IEEE Transactions on Nanotechnology 21 (2022), 728\u2013736.","journal-title":"IEEE Transactions on Nanotechnology"},{"key":"e_1_3_1_13_2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2884646"},{"key":"e_1_3_1_14_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2889770"},{"key":"e_1_3_1_15_2","doi-asserted-by":"publisher","DOI":"10.1149\/1.3567706"},{"key":"e_1_3_1_16_2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2359385"},{"key":"e_1_3_1_17_2","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2021.3092167"},{"key":"e_1_3_1_18_2","first-page":"1","volume-title":"Proceedings of the 2017 IEEE International Conference on Rebooting Computing (ICRC)","author":"Cheng K.","year":"2017","unstructured":"K. Cheng, S. Le Beux, and I. O\u2019Connor. 2017. Hybrid topologies for reconfigurable matrices based on nano-grain cells. In Proceedings of the 2017 IEEE International Conference on Rebooting Computing (ICRC). IEEE, 1\u20138."},{"key":"e_1_3_1_19_2","doi-asserted-by":"publisher","DOI":"10.5555\/2971808.2971846"},{"key":"e_1_3_1_20_2","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/3388617","article-title":"VTR 8: High-performance CAD and customizable FPGA architecture modelling","volume":"13","author":"Murray Kevin E.","year":"2020","unstructured":"Kevin E. Murray, Oleg Petelin, Sheng Zhong, Jia Min Wang, Mohamed Eldafrawy, Jean-Philippe Legault, Eugene Sha, Aaron G. Graham, Jean Wu, Matthew J. P. Walker, et al. 2020. VTR 8: High-performance CAD and customizable FPGA architecture modelling. ACM Transactions on Reconfigurable Technology Systems 13 (2020), 1\u201355.","journal-title":"ACM Transactions on Reconfigurable Technology Systems"},{"key":"e_1_3_1_21_2","doi-asserted-by":"publisher","DOI":"10.1007\/s00500-016-2474-6"},{"key":"e_1_3_1_22_2","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2015.2398218"},{"key":"e_1_3_1_23_2","doi-asserted-by":"publisher","DOI":"10.1088\/1361-6641\/aa5581"},{"key":"e_1_3_1_24_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.sse.2022.108381"},{"key":"e_1_3_1_25_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2014.2333675"},{"key":"e_1_3_1_26_2","first-page":"1","volume-title":"Proceedings of the 2018 76th Device Research Conference (DRC)","author":"Simon M.","year":"2018","unstructured":"M. Simon, J. Trommer, B. Liang, D. Fischer, T. Baldauf, M. B. Khan, A. Heinzig, M. Knaut, Y. M. Georgiev, and A. Erbe. 2018. A wired-AND transistor: Polarity controllable FET with multiple inputs. In Proceedings of the 2018 76th Device Research Conference (DRC). IEEE, 1\u20132."},{"key":"e_1_3_1_27_2","first-page":"338","volume-title":"Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE)","author":"Raitza M.","year":"2017","unstructured":"M. Raitza, A. Kumar, M. V\u00f6lp, D. Walter, J. Trommer, T. Mikolajick, and W. M. Weber. 2017. Exploiting transistor-level reconfiguration to optimize combinational circuits. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE). IEEE, 338\u2013343."},{"key":"e_1_3_1_28_2","first-page":"172","volume-title":"Proceedings of the 2019 IFIP\/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC)","author":"Gore G.","year":"2019","unstructured":"G. Gore, P. Cadareanu, E. Giacomin, and P.-E. Gaillardon. 2019. A predictive process design kit for three-independent-gate field-effect transistors. In Proceedings of the 2019 IFIP\/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC). IEEE, 172\u2013177."},{"key":"e_1_3_1_29_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2016.04.006"},{"key":"e_1_3_1_30_2","doi-asserted-by":"publisher","DOI":"10.1109\/JEDS.2021.3070475"},{"key":"e_1_3_1_31_2","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2017.2710236"},{"key":"e_1_3_1_32_2","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2020.2973004"},{"issue":"5","key":"e_1_3_1_33_2","doi-asserted-by":"crossref","first-page":"2849","DOI":"10.1109\/TED.2024.3375829","article-title":"TCAD simulations of reconfigurable field-effect transistor with embedded-fin-contact to improve on-current","volume":"71","author":"Wang C.","year":"2024","unstructured":"C. Wang, J. Hu, Z. Liu, X. Li, Y. Shi, and Y. Sun. 2024. TCAD simulations of reconfigurable field-effect transistor with embedded-fin-contact to improve on-current. IEEE Transactions on Electron Devices 71, 5 (2024), 2849\u20132855.","journal-title":"IEEE Transactions on Electron Devices"},{"key":"e_1_3_1_34_2","first-page":"1","volume-title":"Proceedings of the 2013 23rd International Conference on Field Programmable Logic and Applications","author":"Chiasson C.","year":"2013","unstructured":"C. Chiasson and V. Betz. 2013. Should FPGAs abandon the pass-gate? In Proceedings of the 2013 23rd International Conference on Field Programmable Logic and Applications. IEEE, 1\u20138."},{"key":"e_1_3_1_35_2","first-page":"1","volume-title":"Proceedings of the Design Automation and Test in Europe Conference","author":"Meijer M.","year":"2006","unstructured":"M. Meijer, R. Krishnan, and M. Bennebroek. 2006. Energy-efficient FPGA interconnect design. In Proceedings of the Design Automation and Test in Europe Conference. IEEE, 1\u20136."},{"key":"e_1_3_1_36_2","first-page":"1","volume-title":"Proceedings of the IEEE Custom Integrated Circuits Conference 2010","author":"Ryan J. F.","year":"2010","unstructured":"J. F. Ryan and B. H. Calhoun. 2010. A sub-threshold FPGA with low-swing dual-VDD interconnect in 90nm CMOS. In Proceedings of the IEEE Custom Integrated Circuits Conference 2010. IEEE, 1\u20134."},{"key":"e_1_3_1_37_2","first-page":"1","volume-title":"Proceedings of the 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","author":"Qi H.","year":"2017","unstructured":"H. Qi, O. Ayorinde, and B. H. Calhoun. 2017. An ultra-low-power FPGA for IoT applications. In Proceedings of the 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S). IEEE, 1\u20133."},{"key":"e_1_3_1_38_2","first-page":"122","volume-title":"Proceedings of the 12th International Conference on Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream (FPL \u201902)","author":"Lemieux G. G.","year":"2002","unstructured":"G. G. Lemieux and D. M. Lewis. 2002. Analytical framework for switch block design. In Proceedings of the 12th International Conference on Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream (FPL \u201902). Springer, 122\u2013131."},{"key":"e_1_3_1_39_2","doi-asserted-by":"crossref","first-page":"250","DOI":"10.1109\/LED.2013.2291783","article-title":"A proposal for a novel hybrid interconnect technology for the end of roadmap","volume":"35","author":"Pan C.","year":"2013","unstructured":"C. Pan and A. Naeemi. 2013. A proposal for a novel hybrid interconnect technology for the end of roadmap. IEEE Electron Device Letters 35 (2013), 250\u2013252.","journal-title":"IEEE Electron Device Letters"},{"key":"e_1_3_1_40_2","doi-asserted-by":"publisher","DOI":"10.1109\/MCAS.2021.3071607"},{"key":"e_1_3_1_41_2","doi-asserted-by":"crossref","first-page":"107","DOI":"10.1145\/368640.368739","volume-title":"Proceedings of the 2001 International Workshop on System-Level Interconnect Prediction","author":"Rahman A.","year":"2001","unstructured":"A. Rahman, S. Das, A. Chandraksan, and R. Reif. 2001. Of conference. Wiring requirement and three-dimensional integration of field-programmable gate arrays. In Proceedings of the 2001 International Workshop on System-Level Interconnect Prediction. ACM, 107\u2013113."},{"key":"e_1_3_1_42_2","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2010.31"},{"key":"e_1_3_1_43_2","first-page":"24","volume-title":"Proceedings of the 22nd International Conference on Computer Aided Verification (CAV \u201910)","author":"Brayton R.","year":"2010","unstructured":"R. Brayton and A. Mishchenko. 2010. ABC: An academic industrial-strength verification tool. In Proceedings of the 22nd International Conference on Computer Aided Verification (CAV \u201910). Springer, 24\u201340."},{"key":"e_1_3_1_44_2","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2020.3045689"},{"key":"e_1_3_1_45_2","doi-asserted-by":"crossref","first-page":"1660","DOI":"10.1109\/ISCAS.2014.6865471","volume-title":"Proceedings of the 2014 IEEE International Symposium on Circuits and Systems (ISCAS)","author":"Tang X.","year":"2014","unstructured":"X. Tang, J. Zhang, P.-E. Gaillardon, and G. De Micheli. 2014. TSPC flip-flop circuit design with three-independent-gate silicon nanowire FETs. In Proceedings of the 2014 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 1660\u20131663."},{"key":"e_1_3_1_46_2","first-page":"1","volume-title":"Proceedings of the 2015 Silicon Nanoelectronics Workshop (SNW)","author":"Wang J.","year":"2015","unstructured":"J. Wang, G. Du, and X. Liu. 2015. Invetigation of reconfigurable silicon nanowire Schottky Barrier transistors-based logic gate circuits and SRAM cell. In Proceedings of the 2015 Silicon Nanoelectronics Workshop (SNW). IEEE, 1\u20132."},{"key":"e_1_3_1_47_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2020.104815"},{"key":"e_1_3_1_48_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2023.3275983"},{"key":"e_1_3_1_49_2","doi-asserted-by":"crossref","unstructured":"A. Boutros A. Arora and V. Betz. 2024. Field-programmable gate array architecture for deep learning: Survey & future directions. arXiv:2404.10076. Retrieved from https:\/\/arxiv.org\/abs\/2404.10076","DOI":"10.1007\/978-981-97-9314-3_49"}],"container-title":["ACM Journal on Emerging Technologies in Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3750730","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,9,12]],"date-time":"2025-09-12T00:22:14Z","timestamp":1757636534000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3750730"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,7,31]]},"references-count":48,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2025,7,31]]}},"alternative-id":["10.1145\/3750730"],"URL":"https:\/\/doi.org\/10.1145\/3750730","relation":{},"ISSN":["1550-4832","1550-4840"],"issn-type":[{"value":"1550-4832","type":"print"},{"value":"1550-4840","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,7,31]]},"assertion":[{"value":"2024-08-23","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2025-07-08","order":2,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2025-09-11","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}