{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,16]],"date-time":"2025-09-16T17:20:19Z","timestamp":1758043219821,"version":"3.44.0"},"reference-count":25,"publisher":"Association for Computing Machinery (ACM)","issue":"3","content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2025,7,31]]},"abstract":"<jats:p>\n            Multi-tenant Field-programmable Gate Arrays (FPGAs) in cloud service are vulnerable to remotely exploitable attacks, among which power waster circuit (PWC)-based fault attacks have been demonstrated as a highly feasible one. PWC generates high switching activities and causes a sudden voltage drop in the power distribution network (PDN), resulting in a delay of signal propagation and FPGA malfunction. Existing countermeasures deploy bitstream checking methodologies or deploy numerous on-chip sensors to mitigate voltage-drop attacks. Since new PWCs without combinatorial loops and a multi-source attack are emerging, the current countermeasures lack the ability to mitigate new security challenges in multi-tenant FPGAs. To address these issues, a Signal-slowdown (SS)-based fault attack mitigation (S\n            <jats:sup>2<\/jats:sup>\n            FAM) method is proposed to detect both combinatorial (ring-oscillator (RO)-based PWC) and non-combinatorial (ring-oscillator Flip-flop (ROFF)-based PWC) loop-based attacks and precisely pinpoint the attack locations. A new calibration technique in S\n            <jats:sup>2<\/jats:sup>\n            FAM facilitates to identify and remove unstable sensor data, thus significantly reducing false positives. Moreover, the proposed method localizes both the single- and multi-source attacks in the FPGA by utilizing a tenant-level SS ranking (TSSR)-based algorithm. Experimental results show that the proposed method reduces the false alarm by 45.8%, compared to the existing works. Our proposed algorithm for attack localization achieves a 100% success rate and reduces the attack localization area for a multi-source attack by 25.2% than an existing countermeasure. The successful localization is achieved by utilizing our proposed method within 2\n            <jats:inline-formula content-type=\"math\/tex\">\n              <jats:tex-math notation=\"LaTeX\" version=\"MathJax\">\\(\\mu\\)<\/jats:tex-math>\n            <\/jats:inline-formula>\n            s (200 clock cycles) of attack duration. The proposed signal slowdown metric with the calibration process reduces the number of on-chip sensors by 78% and the localization time by 90.5%, compared to the baseline.\n          <\/jats:p>","DOI":"10.1145\/3756013","type":"journal-article","created":{"date-parts":[[2025,9,12]],"date-time":"2025-09-12T00:22:08Z","timestamp":1757636528000},"page":"1-25","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["S\n            <sup>2<\/sup>\n            FAM: Signal-slowdown-based Fault Attack Mitigation Method for Secure Multi-tenant FPGA"],"prefix":"10.1145","volume":"21","author":[{"ORCID":"https:\/\/orcid.org\/0009-0009-0644-3033","authenticated-orcid":false,"given":"Sandeep","family":"Sunkavilli","sequence":"first","affiliation":[{"name":"Department of Electrical and Computer Engineering, University of New Hampshire, Durham, NH, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6791-1675","authenticated-orcid":false,"given":"Mashrafi Alam","family":"Kajol","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, University of New Hampshire, Durham, NH, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7232-8529","authenticated-orcid":false,"given":"Qiaoyan","family":"Yu","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, University of New Hampshire, Durham, NH, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2025,9,11]]},"reference":[{"key":"e_1_3_1_2_2","doi-asserted-by":"publisher","DOI":"10.1109\/FDTC.2019.00015"},{"key":"e_1_3_1_3_2","unstructured":"Xilinx AMD. 2016. Integrated Logic Analyzer v6.2. Retrieved from https:\/\/docs.amd.com\/v\/u\/en-US\/pg172-ila"},{"key":"e_1_3_1_4_2","unstructured":"Xilinx AMD. 2022. Design Analysis and Closure Techniques. Retrieved from https:\/\/www.xilinx.com\/support\/documents\/sw_manuals\/xilinx2022_1\/ug906-vivado-design-analysis.pdf"},{"key":"e_1_3_1_5_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2021.3111049"},{"key":"e_1_3_1_6_2","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2008.4629939"},{"key":"e_1_3_1_7_2","doi-asserted-by":"publisher","DOI":"10.23919\/FPL.2017.8056840"},{"key":"e_1_3_1_8_2","volume-title":"Xilinx, Inc","author":"Hussein Jameel","year":"2011","unstructured":"Jameel Hussein, Matt Klein, and Michael Hart. 2011. Lowering power at 28 nm with Xilinx 7 series FPGAs. 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In 2023 Asian Hardware Oriented Security and Trust Symposium (AsianHOST)."},{"key":"e_1_3_1_10_2","doi-asserted-by":"publisher","DOI":"10.23919\/DATE51398.2021.9474140"},{"key":"e_1_3_1_11_2","doi-asserted-by":"publisher","DOI":"10.13154\/tches.v2018.i3.44-68"},{"key":"e_1_3_1_12_2","doi-asserted-by":"publisher","DOI":"10.1145\/3328222"},{"key":"e_1_3_1_13_2","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM53951.2022.9786154"},{"key":"e_1_3_1_14_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.procs.2021.02.028"},{"key":"e_1_3_1_15_2","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18074.2021.9586262"},{"key":"e_1_3_1_16_2","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8715263"},{"key":"e_1_3_1_17_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICFPT51103.2020.00050"},{"key":"e_1_3_1_18_2","doi-asserted-by":"publisher","DOI":"10.3390\/app11083330"},{"key":"e_1_3_1_19_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD51958.2021.9643485"},{"key":"e_1_3_1_20_2","doi-asserted-by":"publisher","DOI":"10.1109\/FPL50879.2020.00046"},{"key":"e_1_3_1_21_2","doi-asserted-by":"publisher","DOI":"10.1145\/3451236"},{"key":"e_1_3_1_22_2","article-title":"Xilinx redefines power, performance, and design productivity with three new 28 nm fpga families: Virtex-7, kintex-7, and artix-7 devices","author":"Przybus Brent","year":"2010","unstructured":"Brent Przybus. 2010. Xilinx redefines power, performance, and design productivity with three new 28 nm fpga families: Virtex-7, kintex-7, and artix-7 devices. Xilinx White Paper. 2010.","journal-title":"Xilinx White Paper"},{"key":"e_1_3_1_23_2","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2016.399"},{"key":"e_1_3_1_24_2","doi-asserted-by":"crossref","first-page":"501672","DOI":"10.1155\/2009\/501672","article-title":"Analysis and enhancement of random number generator in FPGA based on oscillator rings","volume":"1","author":"Wold Knut","year":"2009","unstructured":"Knut Wold and Chik How Tan. 2009. Analysis and enhancement of random number generator in FPGA based on oscillator rings. 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