{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,16]],"date-time":"2025-09-16T16:53:12Z","timestamp":1758041592740,"version":"3.44.0"},"reference-count":25,"publisher":"Association for Computing Machinery (ACM)","issue":"5","funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"crossref","award":["92373206, 92473203"],"award-info":[{"award-number":["92373206, 92473203"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/501100004739","name":"Youth Innovation Promotion Association, CAS","doi-asserted-by":"crossref","id":[{"id":"10.13039\/501100004739","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2025,9,30]]},"abstract":"<jats:p>\n            Gate-level fault simulation is essential for automatic test pattern generation (ATPG). The traditional event-driven simulation is time-consuming due to the large number of faults. While parallel fault simulation with GPGPUs shows promise, it faces reduced parallel efficiency on large circuits. This is mainly due to the increased space required to store fault values, limiting the number of faults that can be processed in parallel and preventing full utilization of the GPU\u2019s capabilities. In this study, we propose a memory-efficient fault machine implementation\n            <jats:italic toggle=\"yes\">\n              FM\n              <jats:sub>gpu<\/jats:sub>\n            <\/jats:italic>\n            based on a circular vector, which is tailored for GPU fault simulation with some sacrifices of time efficiency and a variable length limit. We also propose a fully adaptive parallel fault simulation framework based on the CPU-GPU heterogeneous system, which includes two stages on the GPU and performs CPU simulation at the same time. All parameters related to GPU memory optimization and workload balancing in the framework can be adjusted adaptively. The experimental results demonstrate that our method achieves better memory efficiency and speedup compared to the previous GPU fault simulation methods, a maximum speedup of 137.48\u00d7 compared to the baseline open-source simulator with 32 threads, and a maximum speedup of 2.52\u00d7 compared to a 32-thread commercial tool.\n          <\/jats:p>","DOI":"10.1145\/3760777","type":"journal-article","created":{"date-parts":[[2025,8,15]],"date-time":"2025-08-15T10:13:21Z","timestamp":1755252801000},"page":"1-27","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Memory-Efficient and Adaptive Heterogeneous Framework for Gate-Level Fault Simulation"],"prefix":"10.1145","volume":"30","author":[{"ORCID":"https:\/\/orcid.org\/0009-0006-2926-7499","authenticated-orcid":false,"given":"Zhiteng","family":"Chao","sequence":"first","affiliation":[{"name":"the State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences","place":["Beijing, China"]},{"name":"University of the Chinese Academy of Sciences, School of Computer Science and Technology","place":["Beijing, China"]}]},{"ORCID":"https:\/\/orcid.org\/0009-0002-9038-2091","authenticated-orcid":false,"given":"Feng","family":"Gu","sequence":"additional","affiliation":[{"name":"the State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences","place":["Beijing, China"]},{"name":"University of the Chinese Academy of Sciences, School of Computer Science and Technology","place":["Beijing, China"]}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5845-6965","authenticated-orcid":false,"given":"Junying","family":"Huang","sequence":"additional","affiliation":[{"name":"the State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences","place":["Beijing, China"]},{"name":"University of the Chinese Academy of Sciences, School of Computer Science and Technology","place":["Beijing, China"]}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3458-3633","authenticated-orcid":false,"given":"Wenjie","family":"Li","sequence":"additional","affiliation":[{"name":"the State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences","place":["Beijing, China"]}]},{"ORCID":"https:\/\/orcid.org\/0009-0004-7900-1336","authenticated-orcid":false,"given":"Jing","family":"Ye","sequence":"additional","affiliation":[{"name":"the State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences","place":["Beijing, China"]},{"name":"University of the Chinese Academy of Sciences, School of Computer Science and Technology","place":["Beijing, China"]},{"name":"the CASTEST Co., Ltd.","place":["Beijing, China"]}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8082-4218","authenticated-orcid":false,"given":"Huawei","family":"Li","sequence":"additional","affiliation":[{"name":"the State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences","place":["Beijing, China"]},{"name":"University of the Chinese Academy of Sciences, School of Computer Science and Technology","place":["Beijing, China"]},{"name":"the CASTEST Co., Ltd.","place":["Beijing, China"]}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0874-814X","authenticated-orcid":false,"given":"Xiaowei","family":"Li","sequence":"additional","affiliation":[{"name":"the State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences","place":["Beijing, China"]},{"name":"University of the Chinese Academy of Sciences, School of Computer Science and Technology","place":["Beijing, China"]},{"name":"the CASTEST Co., Ltd.","place":["Beijing, China"]}]}],"member":"320","published-online":{"date-parts":[[2025,9,11]]},"reference":[{"unstructured":"CASTEST Co. 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