{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,2]],"date-time":"2025-10-02T00:56:18Z","timestamp":1759366578579,"version":"build-2065373602"},"reference-count":47,"publisher":"Association for Computing Machinery (ACM)","issue":"5s","funder":[{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation","doi-asserted-by":"crossref","award":["2020-IR-2979"],"award-info":[{"award-number":["2020-IR-2979"]}],"id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2025,11,30]]},"abstract":"<jats:p>Contention in shared caches caused by concurrently executing applications can lead to overall performance degradation in multiprocessor systems-on-chip (MPSoCs). To address this issue, various shared cache arbitration techniques have been proposed to manage cache bandwidth contention. These techniques focus on enhancing overall system performance; however, this optimization often comes at the expense of system fairness, leading to some applications experiencing disproportionate slowdowns, or, in the worst case, starvation. Therefore, an effective shared cache bandwidth management policy is needed to optimize performance while ensuring fairness across applications.<\/jats:p>\n          <jats:p>\n            We propose\n            <jats:italic toggle=\"yes\">FARRE<\/jats:italic>\n            , a novel fairness aware request-response arbitration technique for shared caches.\n            <jats:italic toggle=\"yes\">FARRE<\/jats:italic>\n            is designed to optimize performance while attempting to maintain a user-defined fairness threshold. We evaluate its effectiveness through extensive simulations including comparisons against state-of-the-art arbitration schemes. The results show that\n            <jats:italic toggle=\"yes\">FARRE<\/jats:italic>\n            is able to maintain or exceed the input fairness thresholds, and improves system performance over standard fair scheduling policies such as round-robin; the performance improvement is 14% for lower fairness thresholds such as 0.5, and could even gain 5% performance for aggressive thresholds such as 0.9. Additionally, compared to the best performance optimization techniques,\n            <jats:italic toggle=\"yes\">FARRE<\/jats:italic>\n            achieves 81% higher fairness.\n          <\/jats:p>","DOI":"10.1145\/3761811","type":"journal-article","created":{"date-parts":[[2025,8,18]],"date-time":"2025-08-18T11:27:42Z","timestamp":1755516462000},"page":"1-26","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["FARRE: Fairness Aware Request Response Arbitration in Shared Caches"],"prefix":"10.1145","volume":"24","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-3944-9636","authenticated-orcid":false,"given":"Garima","family":"Modi","sequence":"first","affiliation":[{"name":"Computer Science and Engineering, Indian Institute of Technology Delhi","place":["New Delhi, India"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0236-5965","authenticated-orcid":false,"given":"Priyanka","family":"Singla","sequence":"additional","affiliation":[{"name":"Intel Architecture Group, Intel","place":["Bangalore, India"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8398-476X","authenticated-orcid":false,"given":"Neetu","family":"Jindal","sequence":"additional","affiliation":[{"name":"Intel Architecture Group, Intel","place":["Bangalore, India"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0008-8862-9941","authenticated-orcid":false,"given":"Ayan","family":"Mandal","sequence":"additional","affiliation":[{"name":"Intel Architecture Group, Intel","place":["Bangalore, India"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2508-7531","authenticated-orcid":false,"given":"Preeti","family":"Panda","sequence":"additional","affiliation":[{"name":"Computer Science and Engineering, Indian Institute of Technology, Delhi","place":["New Delhi, India"]}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2025,9,26]]},"reference":[{"key":"e_1_3_2_2_2","doi-asserted-by":"publisher","DOI":"10.1145\/3632748"},{"key":"e_1_3_2_3_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2010.19"},{"key":"e_1_3_2_4_2","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2019.00016"},{"key":"e_1_3_2_5_2","doi-asserted-by":"publisher","DOI":"10.23919\/DATE51398.2021.9474096"},{"key":"e_1_3_2_6_2","doi-asserted-by":"publisher","DOI":"10.1145\/1735971.1736058"},{"key":"e_1_3_2_7_2","doi-asserted-by":"publisher","DOI":"10.1080\/17445760.2014.922560"},{"key":"e_1_3_2_8_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2018.00019"},{"key":"e_1_3_2_9_2","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.44"},{"key":"e_1_3_2_10_2","doi-asserted-by":"publisher","DOI":"10.1145\/3632955"},{"key":"e_1_3_2_11_2","doi-asserted-by":"publisher","DOI":"10.1109\/CSO.2010.29"},{"key":"e_1_3_2_12_2","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2015.48"},{"key":"e_1_3_2_13_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2015.2428694"},{"key":"e_1_3_2_14_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2016.2620977"},{"key":"e_1_3_2_15_2","doi-asserted-by":"publisher","DOI":"10.1145\/1186736.1186737"},{"key":"e_1_3_2_16_2","doi-asserted-by":"publisher","DOI":"10.1109\/PACT52795.2021.00023"},{"key":"e_1_3_2_17_2","doi-asserted-by":"publisher","DOI":"10.1145\/2755573.2755581"},{"key":"e_1_3_2_18_2","doi-asserted-by":"publisher","DOI":"10.1145\/1394608.1382172"},{"key":"e_1_3_2_19_2","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2023.3242178"},{"key":"e_1_3_2_20_2","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2004.1342546"},{"key":"e_1_3_2_21_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.3012861"},{"key":"e_1_3_2_22_2","doi-asserted-by":"publisher","DOI":"10.1145\/3524616"},{"key":"e_1_3_2_23_2","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2018.8341983"},{"key":"e_1_3_2_24_2","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2022.3143295"},{"key":"e_1_3_2_25_2","unstructured":"Jason Lowe-Power Abdul Mutaal Ahmad Ayaz Akram Mohammad Alian Rico Amslinger Matteo Andreozzi Adri\u00e0 Armejach Nils Asmussen Brad Beckmann Srikant Bharadwaj et\u00a0al. 2020. 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