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Embed. Comput. Syst."],"published-print":{"date-parts":[[2025,11,30]]},"abstract":"<jats:p>\n                    Multi-chiplet architectures enabled by glass interposer offer superior electrical performance, enable higher bus widths due to reduced crosstalk, and have lower capacitance in the redistribution layer than current silicon interposer-based systems. These advantages result in lower energy per bit, higher communication frequencies, and extended interconnect range. However, deformation of the package (warpage) in glass interposer-based systems becomes a critical challenge as system size increases, leading to severe mechanical stress and reliability concerns. Beyond a certain size, conventional packaging techniques fail to manage warpage effectively, necessitating new approaches to mitigate warpage induced bending with scalable performance for glass interposer based multi-chiplet systems. To address these inter-twined challenges, we propose a thermal-, warpage-, and performance-aware design framework that employs\n                    <jats:bold>architecture and packaging co-optimization<\/jats:bold>\n                    . The proposed framework disintegrates the surface and embedded chiplets to balance conflicting design objectives, ensuring optimal tradeoffs between performance, power, and structural reliability. Our experiments demonstrate that optimized multi-chiplet architectures from our design framework achieve up to\n                    <jats:bold>64.7% performance improvement<\/jats:bold>\n                    and\n                    <jats:bold>40% power reduction<\/jats:bold>\n                    compared to traditional 2.5D systems to execute deep neural network workloads with lower fabrication costs.\n                  <\/jats:p>","DOI":"10.1145\/3762644","type":"journal-article","created":{"date-parts":[[2025,9,4]],"date-time":"2025-09-04T04:14:58Z","timestamp":1756959298000},"page":"1-28","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":9,"title":["Designing High-Performance and Thermally Feasible Multi-Chiplet Architectures Enabled by Non-Bendable Glass Interposer"],"prefix":"10.1145","volume":"24","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-0334-4269","authenticated-orcid":false,"given":"Harsh","family":"Sharma","sequence":"first","affiliation":[{"name":"Washington State University","place":["Pullman, United States"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3848-5301","authenticated-orcid":false,"given":"Jana","family":"Doppa","sequence":"additional","affiliation":[{"name":"Washington State University","place":["Pullman, United States"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5045-5535","authenticated-orcid":false,"given":"Umit","family":"Ogras","sequence":"additional","affiliation":[{"name":"University of Wisconsin-Madison","place":["Madison, United States"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5930-8531","authenticated-orcid":false,"given":"Partha","family":"Pande","sequence":"additional","affiliation":[{"name":"Washington State University","place":["Pullman, United States"]}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2025,9,26]]},"reference":[{"key":"e_1_3_1_2_2","volume-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","unstructured":"Pruek Vanna-Iampikul, Seungmin Woo, Serhat Erdogan, Lingjun Zhu, Mohanalingam Kathaperumal, Ravi Agarwal, Ram Gupta, Kevin Rinebold, Madhavan Swaminathan, and Sung Kyu Lim. 2024. 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