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Embed. Comput. Syst."],"published-print":{"date-parts":[[2025,11,30]]},"abstract":"<jats:p>\n            Runahead execution is a technique to mask memory latency caused by irregular memory accesses. By pre-executing the application code during occurrences of long-latency operations and prefetching anticipated cache-missed data into the cache hierarchy, runahead effectively masks memory latency for subsequent cache misses and achieves high prefetching accuracy; however, this technique has been limited to superscalar out-of-order and superscalar in-order cores. For implementation in scalar in-order cores, the challenges of area-\/energy-constraint and severe cache contention remain. Here, we build the first full-stack system featuring runahead,\n            <jats:monospace>MERE<\/jats:monospace>\n            , from SoC and a dedicated ISA to the OS and programming model. Through this deployment, we show that enabling runahead in scalar in-order cores is possible, with minimal area and power overheads, while still achieving high performance. By re-constructing the sequential runahead employing a hardware\/software co-design approach, the system can be implemented on a mature processor and SoC. Building on this, an adaptive runahead mechanism is proposed to mitigate the severe cache contention in scalar in-order cores. Combining this, we provide a comprehensive solution for embedded processors managing irregular workloads. Our evaluation demonstrates that the proposed\n            <jats:monospace>MERE<\/jats:monospace>\n            attains 93.5% of a 2-wide out-of-order core\u2019s performance while constraining area and power overheads below 5%, with the adaptive runahead mechanism delivering an additional 20.1% performance gain through mitigating the severe cache contention issues.\n          <\/jats:p>","DOI":"10.1145\/3762654","type":"journal-article","created":{"date-parts":[[2025,8,27]],"date-time":"2025-08-27T11:51:58Z","timestamp":1756295518000},"page":"1-26","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["MERE: Hardware-Software Co-Design for Masking Cache Miss Latency in Embedded Processors"],"prefix":"10.1145","volume":"24","author":[{"ORCID":"https:\/\/orcid.org\/0009-0002-4588-3794","authenticated-orcid":false,"given":"Dean","family":"You","sequence":"first","affiliation":[{"name":"National Center of Technology Innovation for EDA, Southeast University","place":["Nanjing, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0001-6629-4967","authenticated-orcid":false,"given":"Jieyu","family":"Jiang","sequence":"additional","affiliation":[{"name":"Sun Yat-Sen University","place":["Guangzhou, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0009-3757-3375","authenticated-orcid":false,"given":"Xiaoxuan","family":"Wang","sequence":"additional","affiliation":[{"name":"National Center of Technology Innovation for EDA, Southeast University","place":["Nanjing, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0008-1951-7698","authenticated-orcid":false,"given":"Yushu","family":"Du","sequence":"additional","affiliation":[{"name":"National Center of Technology Innovation for EDA, Southeast University","place":["Nanjing, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0009-9265-1065","authenticated-orcid":false,"given":"Zhihang","family":"Tan","sequence":"additional","affiliation":[{"name":"National Center of Technology Innovation for EDA, Southeast University","place":["Nanjing, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0008-4912-1280","authenticated-orcid":false,"given":"Wenbo","family":"Xu","sequence":"additional","affiliation":[{"name":"Huazhong University of Science and Technology","place":["Wuhan, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0000-4078-6667","authenticated-orcid":false,"given":"Hui","family":"Wang","sequence":"additional","affiliation":[{"name":"National Center of Technology Innovation for EDA, Southeast University","place":["Nanjing, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0006-6850-8785","authenticated-orcid":false,"given":"Jiapeng","family":"Guan","sequence":"additional","affiliation":[{"name":"computer, Dalian University of Technology","place":["Dalian, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2191-1359","authenticated-orcid":false,"given":"Ran","family":"Wei","sequence":"additional","affiliation":[{"name":"Computing and Communications, Lancaster University","place":["Lancaster, United Kingdom of Great Britain and Northern Ireland"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0721-8021","authenticated-orcid":false,"given":"Shuai","family":"Zhao","sequence":"additional","affiliation":[{"name":"Sun Yat-Sen University","place":["Guangzhou, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8509-3167","authenticated-orcid":false,"given":"Zhe","family":"Jiang","sequence":"additional","affiliation":[{"name":"Southeast University","place":["Nanjing, China"]},{"name":"Computer Science, University of York","place":["Nanjing, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2025,9,26]]},"reference":[{"key":"e_1_3_2_2_2","doi-asserted-by":"publisher","DOI":"10.5555\/3049832.3049865"},{"key":"e_1_3_2_3_2","doi-asserted-by":"publisher","DOI":"10.1145\/3296957.3173189"},{"key":"e_1_3_2_4_2","article-title":"ARM Cortex-M3 Processor","year":"2004","unstructured":"ARM. 2004. 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