{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T02:46:20Z","timestamp":1781837180956,"version":"3.54.5"},"publisher-location":"New York, NY, USA","reference-count":38,"publisher":"ACM","content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2026,3,15]]},"DOI":"10.1145\/3764386.3779577","type":"proceedings-article","created":{"date-parts":[[2026,3,27]],"date-time":"2026-03-27T18:57:27Z","timestamp":1774637847000},"page":"153-161","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["CHASE: A\n                    <u>CH<\/u>\n                    iplet\n                    <u>A<\/u>\n                    rchitecture\n                    <u>S<\/u>\n                    imulation and\n                    <u>E<\/u>\n                    xploration Framework with Decoupled Multi-Fidelity Optimization"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-9401-0482","authenticated-orcid":false,"given":"Shixin","family":"Chen","sequence":"first","affiliation":[{"name":"The Chinese University of Hong Kong, Shatin, Hong Kong"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0009-4019-8625","authenticated-orcid":false,"given":"Hengyuan","family":"Zhang","sequence":"additional","affiliation":[{"name":"Beijing University of Posts and Telecommunications, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1581-3536","authenticated-orcid":false,"given":"Jianwang","family":"Zhai","sequence":"additional","affiliation":[{"name":"Beijing University of Posts and Telecommunications, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6406-4810","authenticated-orcid":false,"given":"Bei","family":"Yu","sequence":"additional","affiliation":[{"name":"The Chinese University of Hong Kong, Shatin, Hong Kong"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2026,3,27]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.1998.658762"},{"issue":"4","key":"e_1_3_2_1_2_1","first-page":"5","article-title":"Silicon cmos devices beyond scaling","volume":"50","author":"Haensch W.","year":"2006","unstructured":"W. Haensch, E. J. Nowak, R. H. Dennard et al., ''Silicon cmos devices beyond scaling,'' IBM Journal of Research and Development, vol. 50, no. 4.5, pp. 339-361, 2006.","journal-title":"IBM Journal of Research and Development"},{"key":"e_1_3_2_1_3_1","volume-title":"The survey of chiplet-based integrated architecture: An eda perspective,'' arXiv preprint arXiv:2411.04410","author":"Chen S.","year":"2024","unstructured":"S. Chen, H. Zhang, Z. Ling, J. Zhai, and B. Yu, ''The survey of chiplet-based integrated architecture: An eda perspective,'' arXiv preprint arXiv:2411.04410, 2024."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/3658617.3703134"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/3489517.3530428"},{"key":"e_1_3_2_1_6_1","first-page":"1","volume-title":"Kite: A family of heterogeneous interposer topologies enabled via accurate interconnect modeling,'' in ACM\/IEEE Design Automation Conference (DAC). hskip 1em plus 0.5em minus 0.4emrelax IEEE","author":"Bharadwaj S.","year":"2020","unstructured":"S. Bharadwaj, J. Yin, B. Beckmann, and T. Krishna, ''Kite: A family of heterogeneous interposer topologies enabled via accurate interconnect modeling,'' in ACM\/IEEE Design Automation Conference (DAC). hskip 1em plus 0.5em minus 0.4emrelax IEEE, 2020, pp. 1-6."},{"key":"e_1_3_2_1_7_1","first-page":"1","article-title":"Hexamesh: Scaling to hundreds of chiplets with an optimized chiplet arrangement","author":"Iff P.","year":"2023","unstructured":"P. Iff, M. Besta, M. Cavalcante et al., ''Hexamesh: Scaling to hundreds of chiplets with an optimized chiplet arrangement,'' in ACM\/IEEE Design Automation Conference (DAC), 2023, pp. 1-6.","journal-title":"ACM\/IEEE Design Automation Conference (DAC)"},{"key":"e_1_3_2_1_8_1","article-title":"Floorplet: Performance-aware floorplan framework for chiplet integration","author":"Chen S.","year":"2023","unstructured":"S. Chen, S. Li, Z. Zhuang et al., ''Floorplet: Performance-aware floorplan framework for chiplet integration,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2023.","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2020.2968904"},{"key":"e_1_3_2_1_10_1","first-page":"1246","article-title":"TAP-2.5 D: A thermally-aware chiplet placement methodology for 2.5 D systems","author":"Ma Y.","year":"2021","unstructured":"Y. Ma, L. Delshadtehrani, C. Demirkiran et al., ''TAP-2.5 D: A thermally-aware chiplet placement methodology for 2.5 D systems,'' in IEEE\/ACM Proceedings Design, Automation and Test in Eurpoe (DATE), 2021, pp. 1246-1251.","journal-title":"IEEE\/ACM Proceedings Design, Automation and Test in Eurpoe (DATE)"},{"key":"e_1_3_2_1_11_1","first-page":"1","article-title":"BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration Framework","author":"Bai C.","year":"2021","unstructured":"C. Bai, Q. Sun, J. Zhai et al., ''BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration Framework,'' in IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), 2021, pp. 1-9.","journal-title":"IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2023.3311620"},{"key":"e_1_3_2_1_13_1","first-page":"207","article-title":"SoC-Tuner: An Importance-guided Exploration Framework for DNN-targeting SoC Design","author":"Chen S.","year":"2024","unstructured":"S. Chen, S. Zheng, C. Bai et al., ''SoC-Tuner: An Importance-guided Exploration Framework for DNN-targeting SoC Design,'' in IEEE\/ACM Asia and South Pacific Design Automation Conference (ASPDAC), 2024, pp. 207-212.","journal-title":"IEEE\/ACM Asia and South Pacific Design Automation Conference (ASPDAC)"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2017.2737644"},{"key":"e_1_3_2_1_15_1","first-page":"44","article-title":"2.2 amd chiplet architecture for high-performance server and desktop products","author":"Naffziger S.","year":"2020","unstructured":"S. Naffziger, K. Lepak, M. Paraschou, and M. Subramony, ''2.2 amd chiplet architecture for high-performance server and desktop products,'' in IEEE International Solid-State Circuits Conference (ISSCC), 2020, pp. 44-45.","journal-title":"IEEE International Solid-State Circuits Conference (ISSCC)"},{"key":"e_1_3_2_1_16_1","unstructured":"N. P. Benchmarks ''Nas parallel benchmarks '' CG and IS 2006."},{"key":"e_1_3_2_1_17_1","unstructured":"BIBentryALTinterwordspacing The gem5 simulator. [Online]. Available: https:\/\/resources.gem5.org\/ BIBentrySTDinterwordspacing"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCPMT.2022.3207195"},{"key":"e_1_3_2_1_19_1","first-page":"9","article-title":"Bunch of wires: An open die-to-die interface","author":"Ardalan S.","year":"2020","unstructured":"S. Ardalan, H. Cirit, R. Farjad et al., ''Bunch of wires: An open die-to-die interface,'' in Proc. HOTI, 2020, pp. 9-16.","journal-title":"Proc. HOTI"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2020.3015494"},{"issue":"1","key":"e_1_3_2_1_21_1","article-title":"The mcpat framework for multicore and manycore architectures: Simultaneously modeling power, area, and timing","volume":"10","author":"Li S.","year":"2013","unstructured":"S. Li, J. H. Ahn, R. D. Strong et al., ''The mcpat framework for multicore and manycore architectures: Simultaneously modeling power, area, and timing,'' ACM Transactions on Architecture and Code Optimization (TACO), vol. 10, no. 1, 2013.","journal-title":"ACM Transactions on Architecture and Code Optimization (TACO)"},{"key":"e_1_3_2_1_22_1","first-page":"1","article-title":"McPAT-Calib: A microarchitecture power modeling framework for modern CPUs","author":"Zhai J.","year":"2021","unstructured":"J. Zhai, C. Bai, B. Zhu et al., ''McPAT-Calib: A microarchitecture power modeling framework for modern CPUs,'' in IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), 2021, pp. 1-9.","journal-title":"IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)"},{"key":"e_1_3_2_1_23_1","first-page":"317","article-title":"Chip\/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs","author":"Jung M.","year":"2012","unstructured":"M. Jung, D. Z. Pan, and S. K. Lim, ''Chip\/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs,'' in ACM\/IEEE Design Automation Conference (DAC), 2012, pp. 317-326.","journal-title":"ACM\/IEEE Design Automation Conference (DAC)"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.876103"},{"key":"e_1_3_2_1_25_1","first-page":"1","volume-title":"Heterogeneous integration of chiplets: cost and yield tradeoff analysis,'' in Proc. EuroSIME. hskip 1em plus 0.5em minus 0.4emrelax IEEE","author":"Ahmad M.","year":"2022","unstructured":"M. Ahmad, J. DeLaCruz, and A. Ramamurthy, ''Heterogeneous integration of chiplets: cost and yield tradeoff analysis,'' in Proc. EuroSIME. hskip 1em plus 0.5em minus 0.4emrelax IEEE, 2022, pp. 1-9."},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2017.2780239"},{"key":"e_1_3_2_1_27_1","first-page":"58","volume-title":"Zhu et al., ''A systematic methodology for characterizing scalability of dnn accelerators using scale-sim","author":"Samajdar A.","year":"2020","unstructured":"A. Samajdar, J. M. Joseph, Y. Zhu et al., ''A systematic methodology for characterizing scalability of dnn accelerators using scale-sim,'' 2020, pp. 58-68."},{"key":"e_1_3_2_1_28_1","first-page":"99","article-title":"A deep reinforcement learning framework for architectural exploration: A routerless noc case study","author":"Lin T.-R.","year":"2020","unstructured":"T.-R. Lin, D. Penney, M. Pedram et al., ''A deep reinforcement learning framework for architectural exploration: A routerless noc case study,'' in IEEE International Symposium on High Performance Computer Architecture (HPCA), 2020, pp. 99-110.","journal-title":"IEEE International Symposium on High Performance Computer Architecture (HPCA)"},{"key":"e_1_3_2_1_29_1","first-page":"40","article-title":"AutoDNNchip: An Automated DNN Chip Predictor and Builder for Both FPGAs and ASICs","author":"Xu P.","year":"2020","unstructured":"P. Xu, X. Zhang, C. Hao et al., ''AutoDNNchip: An Automated DNN Chip Predictor and Builder for Both FPGAs and ASICs,'' in ACM International Symposium on Field-Programmable Gate Arrays (FPGA), 2020, p. 40\u201350.","journal-title":"ACM International Symposium on Field-Programmable Gate Arrays (FPGA)"},{"key":"e_1_3_2_1_30_1","first-page":"1492","article-title":"Predictive entropy search for multi-objective bayesian optimization","author":"Hern\u00e1ndez-Lobato D.","year":"2016","unstructured":"D. Hern\u00e1ndez-Lobato, J. Hernandez-Lobato, A. Shah et al., ''Predictive entropy search for multi-objective bayesian optimization,'' in International Conference on Machine Learning (ICML), 2016, pp. 1492-1501.","journal-title":"International Conference on Machine Learning (ICML)"},{"key":"e_1_3_2_1_31_1","first-page":"7167","article-title":"Hypervolume knowledge gradient: a lookahead approach for multi-objective bayesian optimization with partial information","author":"Daulton S.","year":"2023","unstructured":"S. Daulton, M. Balandat, and E. Bakshy, ''Hypervolume knowledge gradient: a lookahead approach for multi-objective bayesian optimization with partial information,'' in International Conference on Machine Learning (ICML), 2023, pp. 7167-7204.","journal-title":"International Conference on Machine Learning (ICML)"},{"key":"e_1_3_2_1_32_1","first-page":"3306","volume-title":"Batch Bayesian optimization via multi-objective acquisition ensemble for automated analog circuit design,'' in International conference on machine learning. hskip 1em plus 0.5em minus 0.4emrelax PMLR","author":"Lyu W.","year":"2018","unstructured":"W. Lyu, F. Yang, C. Yan, D. Zhou, and X. Zeng, ''Batch Bayesian optimization via multi-objective acquisition ensemble for automated analog circuit design,'' in International conference on machine learning. hskip 1em plus 0.5em minus 0.4emrelax PMLR, 2018, pp. 3306-3314."},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/CEC.2011.5949880"},{"key":"e_1_3_2_1_34_1","first-page":"1","article-title":"Multi-package co-design for chiplet integration","author":"Zhuang Z.","year":"2022","unstructured":"Z. Zhuang, B. Yu, K.-Y. Chao et al., ''Multi-package co-design for chiplet integration,'' in IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), 2022, pp. 1-9.","journal-title":"IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)"},{"key":"e_1_3_2_1_35_1","first-page":"1","article-title":"and signal assignment for silicon interposer-based 3D ICs","author":"Liu W.-H.","year":"2014","unstructured":"W.-H. Liu, M.-S. Chang, and T.-C. Wang, ''Floorplanning and signal assignment for silicon interposer-based 3D ICs,'' in ACM\/IEEE Design Automation Conference (DAC), 2014, pp. 1-6.","journal-title":"ACM\/IEEE Design Automation Conference (DAC)"},{"key":"e_1_3_2_1_36_1","first-page":"1","volume-title":"CPU2006 benchmark descriptions,'' ACM SIGARCH Computer Architecture News","volume":"34","author":"Henning J. L.","year":"2006","unstructured":"J. L. Henning, ''SPEC CPU2006 benchmark descriptions,'' ACM SIGARCH Computer Architecture News, vol. 34, no. 4, pp. 1-17, 2006."},{"key":"e_1_3_2_1_37_1","first-page":"340","article-title":"Illustrative design space studies with microarchitectural regression models","author":"Lee B. C.","year":"2007","unstructured":"B. C. Lee and D. M. Brooks, ''Illustrative design space studies with microarchitectural regression models,'' in IEEE International Symposium on High Performance Computer Architecture (HPCA), 2007, pp. 340-351.","journal-title":"IEEE International Symposium on High Performance Computer Architecture (HPCA)"},{"key":"e_1_3_2_1_38_1","first-page":"785","article-title":"Xgboost: A scalable tree boosting system","author":"Chen T.","year":"2016","unstructured":"T. Chen et al., ''Xgboost: A scalable tree boosting system,'' in Proceedings of International Conference on Knowledge Discovery and Data Mining (KDD), 2016, pp. 785-794.","journal-title":"Proceedings of International Conference on Knowledge Discovery and Data Mining (KDD)"}],"event":{"name":"ISPD '26: International Symposium on Physical Design","location":"Bonn Germany","sponsor":["SIGDA ACM Special Interest Group on Design Automation"]},"container-title":["Proceedings of the 2026 International Symposium on Physical Design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3764386.3779577","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,3,27]],"date-time":"2026-03-27T18:58:49Z","timestamp":1774637929000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3764386.3779577"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,3,15]]},"references-count":38,"alternative-id":["10.1145\/3764386.3779577","10.1145\/3764386"],"URL":"https:\/\/doi.org\/10.1145\/3764386.3779577","relation":{},"subject":[],"published":{"date-parts":[[2026,3,15]]},"assertion":[{"value":"2026-03-27","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}