{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,27]],"date-time":"2026-03-27T19:49:49Z","timestamp":1774640989057,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":59,"publisher":"ACM","license":[{"start":{"date-parts":[[2027,3,27]],"date-time":"2027-03-27T00:00:00Z","timestamp":1806105600000},"content-version":"vor","delay-in-days":377,"URL":"http:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"National Science Foundation","award":["2437795, 2212345"],"award-info":[{"award-number":["2437795, 2212345"]}]},{"name":"SRC JUMP 2.0","award":["-"],"award-info":[{"award-number":["-"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2026,3,15]]},"DOI":"10.1145\/3764386.3780044","type":"proceedings-article","created":{"date-parts":[[2026,3,27]],"date-time":"2026-03-27T18:57:27Z","timestamp":1774637847000},"page":"191-199","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Invited: Toward Accurate, Large-scale Electromigration Analysis and Optimization in Integrated Systems"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-5353-2364","authenticated-orcid":false,"given":"Sachin S.","family":"Sapatnekar","sequence":"first","affiliation":[{"name":"University of Minnesota, Minneapolis, MN, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2026,3,27]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2005.853507"},{"key":"e_1_3_2_1_2_1","volume-title":"Proc. IEDM. IEEE","author":"C. Auth","year":"2017","unstructured":"C. Auth et al., 2017. A 10nm high performance and low-power CMOS technology featuring 3$^rm rd$ generation FinFET transistors, self-aligned quad patterning, contact over active gate and cobalt local interconnects. In Proc. IEDM. IEEE, Piscataway, NJ, 29.1.1-29.1.4."},{"key":"e_1_3_2_1_3_1","volume-title":"Proc. ICCAD. ACM","author":"Axelou O.","unstructured":"O. Axelou, N. Evmorfopoulos, G. Floros, G. Stamoulis, and S. S. Sapatnekar. 2022. A novel semi-analytical approach for fast electromigration stress analysis in multi-segment interconnects. In Proc. ICCAD. ACM, New York, NY."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1969.7340"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.322842"},{"key":"e_1_3_2_1_6_1","unstructured":"M. Celik L.T. Pileggi and A. Odabasioglu. 2002. IC Interconnect Analysis. Kluwer Boston MA."},{"key":"e_1_3_2_1_7_1","first-page":"540","volume-title":"Proc. ICCAD. IEEE","author":"Chatterjee S.","unstructured":"S. Chatterjee, M. Fawaz, and F.N. Najm. 2013. Redundancy-aware electromigration checking for mesh power grids. In Proc. ICCAD. IEEE, Piscataway, NJ, 540-547."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2666723"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2016.2523898"},{"key":"e_1_3_2_1_10_1","volume-title":"ACM T. Des. Automat. El.","volume":"28","author":"Chhabria V. A.","year":"2022","unstructured":"V. A. Chhabria, V. Ahuja, A. Prabhu, N. Patil, P. Jain, and S. S. Sapatnekar. 2022. Encoder-decoder networks for analyzing thermal and power delivery networks. ACM T. Des. Automat. El., Vol. 28, 1, Article 3 (dec 2022), 27 pages."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2800707"},{"key":"e_1_3_2_1_12_1","volume-title":"Proc. IRPS. IEEE","author":"Demircan E.","unstructured":"E. Demircan and M. Shroff. 2014. Model based method for electro-migration stress determination in interconnects. In Proc. IRPS. IEEE, Piscataway, NJ, IT5.1-IT5.6."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/RELPHY.2001.922923"},{"key":"e_1_3_2_1_14_1","volume-title":"Proc. IRPS. IEEE","author":"Gibson P.","unstructured":"P. Gibson, M. Hogan, and V. Sukharev. 2014. Electromigration analysis of full-chip integrated circuits with hydrostatic stress. In Proc. IRPS. IEEE, Piscataway, NJ, IT2.1-IT2.7."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1016\/0022-3697(61)90139-1"},{"key":"e_1_3_2_1_16_1","volume-title":"GNOMO: Greater-than-NOMinal Vdd operation for BTI mitigation. In Proc","author":"Gupta S.","year":"2012","unstructured":"S. Gupta and S. S. Sapatnekar. 2012. GNOMO: Greater-than-NOMinal Vdd operation for BTI mitigation. In Proc. ASP-DAC. IEEE, Piscataway, NJ, 271-276."},{"key":"e_1_3_2_1_17_1","volume-title":"ACM T. Des. Automat. El.","volume":"18","author":"Gupta S.","year":"2013","unstructured":"S. Gupta and S. S. Sapatnekar. 2013. Employing circadian rhythms to enhance power and reliability. ACM T. Des. Automat. El., Vol. 18, 3, Article 38 (July 2013)."},{"key":"e_1_3_2_1_18_1","volume-title":"Invited: EDA for heterogeneous integration. In Proc","author":"Haque E.","year":"2025","unstructured":"E. Haque, P. Nalla, C. C. Sudarshan, D. Yogi, H. Zhang, C. Chakrabarti, V. A. Chhabria, R. Harjani, J. Zhang, and S. S. Sapatnekar. 2025. Invited: EDA for heterogeneous integration. In Proc. DAC. IEEE, Piscataway, NJ, 4 pages."},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.855941"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/3567424"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.123974"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2016.7428018"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593180"},{"key":"e_1_3_2_1_24_1","first-page":"2","article-title":"Self-consistent solutions for allowed interconnect current density","volume":"44","author":"Hunter W.","year":"1997","unstructured":"W. Hunter. 1997. Self-consistent solutions for allowed interconnect current density. II. IEEE T. Electron Dev., Vol. 44, 2 (Feb. 1997), 310-316.","journal-title":"II. IEEE T. Electron Dev."},{"key":"e_1_3_2_1_25_1","unstructured":"IEEE Components & Packaging Society. 2024. Heterogeneous Integration Roadmap. https:\/\/eps.ieee.org\/technology\/heterogeneous-integration-roadmap.html."},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2505504"},{"key":"e_1_3_2_1_27_1","volume-title":"Proc. IRPS. IEEE","author":"Jain P.","unstructured":"P. Jain, S. S. Sapatnekar, and J. Cortadella. 2015. Stochastic and topologically aware electromigration analysis for clock skew. In Proc. IRPS. IEEE, Piscataway, NJ, 3.D.4-1-3.D.4-6."},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.1995.520712"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.354073"},{"key":"e_1_3_2_1_30_1","volume-title":"Proc. IRPS. IEEE","author":"Kteyan A.","unstructured":"A. Kteyan, V. Sukharev, Y. Yi, and C. Kim. 2022. Novel methodology for temperature-aware electromigration assessment in on-chip power grid: simulations and experimental validation. In Proc. IRPS. IEEE, Piscataway, NJ, 10 pages."},{"key":"e_1_3_2_1_31_1","volume-title":"Proc. DAC. IEEE","author":"Lamichhane S.","year":"2025","unstructured":"S. Lamichhane, M. Kavousi, and S. X.-D. Tan. 2025. BPINN-EM: Fast stochastic analysis of electromigration damage using Bayesian physics-informed neural networks. In Proc. DAC. IEEE, Piscataway, NJ, Article 37, 9 pages."},{"key":"e_1_3_2_1_32_1","first-page":"3","article-title":"Electromigration recovery and short lead effect under bipolar- and unipolar-pulse current. In Proc. IRPS. IEEE, Piscataway","volume":"6","author":"Lee K.-D.","year":"2012","unstructured":"K.-D. Lee. 2012. Electromigration recovery and short lead effect under bipolar- and unipolar-pulse current. In Proc. IRPS. IEEE, Piscataway, NJ, 6B.3.1-6B.3.4.","journal-title":"NJ"},{"key":"e_1_3_2_1_33_1","first-page":"1","article-title":"Statistical evaluation of electromigration reliability at chip level","volume":"11","author":"Li B.","year":"2011","unstructured":"B. Li, P. S. McLaughlin, J. P. Bickford, P.Habitz, D. Netrabile, and T. D. Sullivan. 2011. Statistical evaluation of electromigration reliability at chip level. IEEE T. Device Mater. Rel., Vol. 11, 1 (March 2011), 86-91.","journal-title":"IEEE T. Device Mater. Rel."},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2011.6105387"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"crossref","unstructured":"J. Lienig S. Rothe and M. Thiele. 2025. Fundamentals of Electromigration-Aware Integrated Circuit Design (2 ed.). Springer Cham Switzerland.","DOI":"10.1007\/978-3-031-80023-8"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2017.2682925"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2007.07.094"},{"key":"e_1_3_2_1_38_1","volume-title":"Proc. DAC. ACM","author":"Mishra Vivek","unstructured":"Vivek Mishra, Palkesh Jain, Sravan K. Marella, and Sachin S. Sapatnekar. 2017. Incorporating the Role of Stress on Electromigration in Power Grids with Via Arrays. In Proc. DAC. ACM, New York, NY, 6 pages."},{"key":"e_1_3_2_1_39_1","volume-title":"Proc. DAC. ACM","author":"Mishra V.","unstructured":"V. Mishra and S. S. Sapatnekar. 2013. The impact of electromigration in copper interconnects on power grid integrity. In Proc. DAC. ACM, New York, NY, 6 pages."},{"key":"e_1_3_2_1_40_1","first-page":"1","article-title":"Predicting electromigration mortality under temperature and product lifetime specifications. In Proc. DAC. IEEE, Piscataway","volume":"43","author":"Mishra V.","year":"2016","unstructured":"V. Mishra and S. S. Sapatnekar. 2016. Predicting electromigration mortality under temperature and product lifetime specifications. In Proc. DAC. IEEE, Piscataway, NJ, 43:1-43:6.","journal-title":"NJ"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2019.8720559"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1116\/6.0000476"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2021.114200"},{"key":"e_1_3_2_1_44_1","first-page":"698","volume-title":"Proc. IRPS. IEEE","author":"Park Y. J.","unstructured":"Y. J. Park, P. Jain, and S. Krishnan. 2010. New electromigration validation: Via node vector method. In Proc. IRPS. IEEE, Piscataway, NJ, 698-704."},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1016\/0022-3697(64)90112-X"},{"key":"e_1_3_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.aeue.2025.155909"},{"key":"e_1_3_2_1_47_1","volume-title":"Timing","author":"Sapatnekar S.","unstructured":"S. Sapatnekar. 2004. Timing. Springer, New York, NY."},{"key":"e_1_3_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2003.1198680"},{"key":"e_1_3_2_1_49_1","volume-title":"Proc. ICCAD. IEEE","author":"Al Shohel M. A.","unstructured":"M. A. Al Shohel, V. A. Chhabria, N. Evmorfopoulos, and S. S. Sapatnekar. 2021c. Analytical modeling of transient electromigration stress based on boundary reflections. In Proc. ICCAD. IEEE, Piscataway, NJ, 8 pages."},{"key":"e_1_3_2_1_50_1","volume-title":"Proc. ICCAD. IEEE","author":"Al Shohel M. A.","unstructured":"M. A. Al Shohel, V. A. Chhabria, N. Evmorfopoulos, and S. S. Sapatnekar. 2021 d. Frequency-domain transient electromigration analysis using circuit theory. In Proc. ICCAD. IEEE, Piscataway, NJ, 8 pages."},{"key":"e_1_3_2_1_51_1","volume-title":"ACM T. Des. Automat. El.","volume":"30","author":"Al Shohel M. A.","year":"2025","unstructured":"M. A. Al Shohel, V. A. Chhabria, N. Evmorfopoulos, and S. S. Sapatnekar. 2025. An analytical solution for transient electromigration stress in multisegment straight-line interconnects based on a stress-wave model. ACM T. Des. Automat. El., Vol. 30, 4 (2025), 57:1 - 57:31."},{"key":"e_1_3_2_1_52_1","unstructured":"M. A. Al Shohel V. A. Chhabria and S. S. Sapatnekar. 2021a. A linear-time algorithm for steady-state analysis of electromigration in general interconnects. arXiv:2112.13451."},{"key":"e_1_3_2_1_53_1","volume-title":"Proc. DAC. IEEE","author":"Al Shohel M. A.","unstructured":"M. A. Al Shohel, V. A. Chhabria, and S. S. Sapatnekar. 2021b. A new, computationally efficient `Blech criterion' for immortality in general interconnects. In Proc. DAC. IEEE, Piscataway, NJ, 6 pages."},{"key":"e_1_3_2_1_54_1","doi-asserted-by":"publisher","DOI":"10.1145\/3566097.3567909"},{"key":"e_1_3_2_1_55_1","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2015.2508447"},{"key":"e_1_3_2_1_56_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2801221"},{"key":"e_1_3_2_1_57_1","doi-asserted-by":"publisher","DOI":"10.1145\/2966986.2967083"},{"key":"e_1_3_2_1_58_1","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2019.2956158"},{"key":"e_1_3_2_1_59_1","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2017.2772193"}],"event":{"name":"ISPD '26: International Symposium on Physical Design","location":"Bonn Germany","sponsor":["SIGDA ACM Special Interest Group on Design Automation"]},"container-title":["Proceedings of the 2026 International Symposium on Physical Design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3764386.3780044","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3764386.3780044","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,3,27]],"date-time":"2026-03-27T18:57:42Z","timestamp":1774637862000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3764386.3780044"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,3,15]]},"references-count":59,"alternative-id":["10.1145\/3764386.3780044","10.1145\/3764386"],"URL":"https:\/\/doi.org\/10.1145\/3764386.3780044","relation":{},"subject":[],"published":{"date-parts":[[2026,3,15]]},"assertion":[{"value":"2026-03-27","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}