{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,9,19]],"date-time":"2026-09-19T17:01:16Z","timestamp":1789837276185,"version":"4.0.1"},"reference-count":68,"publisher":"Association for Computing Machinery (ACM)","issue":"1","content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2026,1,31]]},"abstract":"<jats:p>\n                    Rapidly evolving artificial intelligence and machine learning applications require ever-increasing computational capabilities, while monolithic 2D design technologies approach their limits. 2.5D\/3D heterogeneous integration of smaller chiplets using advanced packaging has emerged as a promising paradigm for addressing this limit and meeting performance demands. These approaches offer a significant cost reduction and higher manufacturing yield than monolithic 2D integrated circuits. However, the compact arrangement and high compute density of these systems exacerbate thermal management challenges, potentially compromising performance. Addressing these thermal modeling challenges is critical, especially as system sizes grow and different design stages require varying levels of accuracy and speed. Since no single thermal modeling technique meets all these needs, this article introduces MFIT, a range of\n                    <jats:italic toggle=\"yes\">multi-fidelity thermal models<\/jats:italic>\n                    that effectively balance accuracy and speed. These multi-fidelity models can enable efficient design space exploration and runtime thermal management. Our extensive testing on systems with 16, 36, and 64 2.5D integrated chiplets and 16\u00d73 3D integrated chiplets demonstrates that these models can reduce execution times from days to mere seconds and milliseconds with negligible loss in accuracy.\n                  <\/jats:p>","DOI":"10.1145\/3765905","type":"journal-article","created":{"date-parts":[[2025,9,4]],"date-time":"2025-09-04T11:03:12Z","timestamp":1756983792000},"page":"1-27","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":22,"title":["MFIT : Multi-FIdelity Thermal Modeling for 2.5D and 3D Multi-Chiplet Architectures"],"prefix":"10.1145","volume":"31","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-7905-9843","authenticated-orcid":false,"given":"Lukas","family":"Pfromm","sequence":"first","affiliation":[{"name":"Electrical and Computer Engineering, University of Wisconsin-Madison","place":["Madison, United States"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0000-8585-9241","authenticated-orcid":false,"given":"Alish","family":"Kanani","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, University of Wisconsin-Madison","place":["Madison, United States"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0334-4269","authenticated-orcid":false,"given":"Harsh","family":"Sharma","sequence":"additional","affiliation":[{"name":"EECS, Washington State University","place":["Pullman, United States"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0006-2263-8672","authenticated-orcid":false,"given":"Parth","family":"Solanki","sequence":"additional","affiliation":[{"name":"University of Wisconsin-Madison","place":["Madison, United States"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8517-9649","authenticated-orcid":false,"given":"Eric","family":"Tervo","sequence":"additional","affiliation":[{"name":"University of Wisconsin-Madison","place":["Madison, United States"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2276-4998","authenticated-orcid":false,"given":"Jaehyun","family":"Park","sequence":"additional","affiliation":[{"name":"School of Electrical Engineering, University of Ulsan","place":["Ulsan, Korea (the Republic of)"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3848-5301","authenticated-orcid":false,"given":"Janardhan","family":"Doppa","sequence":"additional","affiliation":[{"name":"Washington State University","place":["Pullman, United States"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5930-8531","authenticated-orcid":false,"given":"Partha Pratim","family":"Pande","sequence":"additional","affiliation":[{"name":"Washington State University","place":["Pullman, United States"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5045-5535","authenticated-orcid":false,"given":"Umit","family":"Ogras","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, University of Wisconsin-Madison","place":["Madison, United States"]}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2025,11,10]]},"reference":[{"key":"e_1_3_2_2_2","unstructured":"BLAS (Basic Linear Algebra Subprograms). Retrieved 26th Nov 2024 from https:\/\/www.netlib.org\/blas\/"},{"key":"e_1_3_2_3_2","unstructured":"2021. Semiconductor Research Corporation \u201cDecadal Plan for Semiconductors\u201d. Retrieved March 31 2024 from https:\/\/www.src.org\/about\/decadal-plan\/decadal-plan-full-report.pdf"},{"key":"e_1_3_2_4_2","unstructured":"2025. Qualcomm\u00ae Profiler. Retrieved April 25 2025 from https:\/\/www.qualcomm.com\/developer\/software\/qualcomm-profiler"},{"key":"e_1_3_2_5_2","doi-asserted-by":"crossref","first-page":"1103","DOI":"10.1109\/ECTC51906.2022.00178","volume-title":"Proceedings of the 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","author":"Agarwal Rahul","year":"2022","unstructured":"Rahul Agarwal, Patrick Cheng, Priyal Shah, Brett Wilkerson, Raja Swaminathan, John Wuu, and Chandrasekhar Mandalapu. 2022. 3D packaging for heterogeneous integration. In Proceedings of the 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC). IEEE, 1103\u20131107."},{"key":"e_1_3_2_6_2","first-page":"347","volume-title":"Proceedings of the IEEE\/ACM ISLPED","author":"Amrouch Hussam","year":"2015","unstructured":"Hussam Amrouch and J\u00f6rg Henkel. 2015. Lucid infrared thermography of thermally-constrained processors. In Proceedings of the IEEE\/ACM ISLPED. 347\u2013352."},{"key":"e_1_3_2_7_2","unstructured":"Semiconductor Industry Association. Intl. Technology Roadmap for Semiconductors 2015 Edition. Retrieved 26th Nov 2024 from https:\/\/www.semiconductors.org\/resources\/2015-Intl.-technology-roadmap-for-semiconductors-itrs\/"},{"key":"e_1_3_2_8_2","doi-asserted-by":"publisher","DOI":"10.5555\/2904830.2904832"},{"key":"e_1_3_2_9_2","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218539"},{"key":"e_1_3_2_10_2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2770163"},{"key":"e_1_3_2_11_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.18"},{"key":"e_1_3_2_12_2","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.58"},{"key":"e_1_3_2_13_2","doi-asserted-by":"publisher","DOI":"10.1115\/1.4050542"},{"issue":"5","key":"e_1_3_2_14_2","first-page":"1232","article-title":"On-chip digital inductor current sensor for monolithic digitally controlled DC-DC converter","volume":"60","author":"Chan Man Pun","year":"2013","unstructured":"Man Pun Chan and Philip K. T. Mok. 2013. On-chip digital inductor current sensor for monolithic digitally controlled DC-DC converter. IEEE Transactions on Circuits and Systems I: Regular Papers 60, 5 (2013), 1232\u20131240.","journal-title":"IEEE Transactions on Circuits and Systems I: Regular Papers"},{"issue":"12","key":"e_1_3_2_15_2","first-page":"3067","article-title":"NeuroSim: A circuit-level macro model for benchmarking neuro-inspired architectures in online learning","volume":"37","author":"Chen Pai-Yu","year":"2018","unstructured":"Pai-Yu Chen, Xiaochen Peng, and Shimeng Yu. 2018. NeuroSim: A circuit-level macro model for benchmarking neuro-inspired architectures in online learning. IEEE TCAD-IC 37, 12 (2018), 3067\u20133080.","journal-title":"IEEE TCAD-IC"},{"key":"e_1_3_2_16_2","first-page":"41.3.1\u201341.3.4","volume-title":"Proceedings of the IEEE IEDM","year":"2020","unstructured":"Y.-K. Cheng, F. Lee, M.-F. Chen, J. Yuan, T.-C. Huang, K.-J. Chen, C.-T. Wang, C.-L. Chen, C.-H. Tsai, and Douglas Yu. 2020. Next-generation design and technology co-optimization (DTCO) of system on integrated chip (SoIC) for mobile and HPC applications. In Proceedings of the IEEE IEDM. 41.3.1\u201341.3.4."},{"key":"e_1_3_2_17_2","first-page":"1","volume-title":"Proceedings of the IEEE\/ACM ISLPED","year":"2017","unstructured":"Pavan Kumar Chundi, Yini Zhou, Martha Kim, Eren Kursun, and Mingoo Seok. 2017. Hotspot monitoring and temperature estimation with miniature on-chip temperature sensors. In Proceedings of the IEEE\/ACM ISLPED. 1\u20136."},{"key":"e_1_3_2_18_2","doi-asserted-by":"crossref","first-page":"125","DOI":"10.1109\/ASSCC.2016.7844151","volume-title":"Proceedings of the 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","author":"Cochet Martin","year":"2016","unstructured":"Martin Cochet, Alberto Puggelli, Ben Keller, Brian Zimmer, Milovan Blagojevic, Sylvain Clerc, Philippe Roche, Jean-Luc Autran, and Borivoje Nikoli\u0107. 2016. On-chip supply power measurement and waveform reconstruction in a 28nm FD-SOI processor SoC. In Proceedings of the 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC). IEEE, 125\u2013128."},{"key":"e_1_3_2_19_2","article-title":"COMSOL Multiphysics Reference Manual","unstructured":"COMSOL. COMSOL Multiphysics Reference Manual. Retrieved 26th Nov. 2024 from https:\/\/comsol.com","journal-title":"Retrieved 26th Nov. 2024 from https:\/\/comsol.com"},{"key":"e_1_3_2_20_2","volume-title":"Proceedings of the WoNDP","author":"Eckert Yasuko","year":"2014","unstructured":"Yasuko Eckert, Nuwan Jayasena, and Gabriel H. Loh. 2014. Thermal feasibility of die-stacked processing in memory. In Proceedings of the WoNDP."},{"key":"e_1_3_2_21_2","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2018.8342238"},{"issue":"1","key":"e_1_3_2_22_2","doi-asserted-by":"crossref","first-page":"13","DOI":"10.1166\/jolpe.2007.106","article-title":"TILTS: A fast architectural-level transient thermal simulation method","volume":"3","author":"Han Yongkui","year":"2007","unstructured":"Yongkui Han, Israel Koren, and C. Mani Krishna. 2007. TILTS: A fast architectural-level transient thermal simulation method. Journal of Low Power Electronics 3, 1 (2007), 13\u201321.","journal-title":"Journal of Low Power Electronics"},{"key":"e_1_3_2_23_2","article-title":"An evaluation framework for dynamic thermal management strategies in 3D multiprocessor system-on-chip co-design","author":"Huang Darong","year":"2024","unstructured":"Darong Huang, Luis Costero, and David Atienza. 2024. An evaluation framework for dynamic thermal management strategies in 3D multiprocessor system-on-chip co-design. IEEE Transactions on Parallel and Distributed Systems 35, 11 (2024), 2161\u20132176.","journal-title":"IEEE Transactions on Parallel and Distributed Systems"},{"issue":"6","key":"e_1_3_2_24_2","doi-asserted-by":"crossref","first-page":"859","DOI":"10.1109\/TCPMT.2023.3289053","article-title":"Experimental study of a two-phase immersion cooling system for the CPU in a PC and a 2U server operated at the overclocking frequency","volume":"13","author":"Huang Shih-Chang","year":"2023","unstructured":"Shih-Chang Huang, Hong-Ping Cheng, Chun-Kai Lo, Yung-Chuan Tseng, and Chin-Chi Cheng. 2023. Experimental study of a two-phase immersion cooling system for the CPU in a PC and a 2U server operated at the overclocking frequency. IEEE Transactions on Components, Packaging and Manufacturing Technology 13, 6 (2023), 859\u2013864.","journal-title":"IEEE Transactions on Components, Packaging and Manufacturing Technology"},{"key":"e_1_3_2_25_2","doi-asserted-by":"crossref","first-page":"165","DOI":"10.1142\/9781860949630_0021","article-title":"The Xyce\u2122 parallel electronic simulator\u2013an overview","author":"Hutchinson S.","year":"2002","unstructured":"S. Hutchinson, E. Keiter, R. Hoekstra, H. Watts, A. Waters, T. Russo, R. Schells, S. Wix, and C. Bogdan. 2002. The Xyce\u2122 parallel electronic simulator\u2013an overview. Parallel Computing: Advances and Current Issues (2002), 165\u2013172.","journal-title":"Parallel Computing: Advances and Current Issues"},{"key":"e_1_3_2_26_2","first-page":"58","volume-title":"Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","author":"Hwang Leslie","year":"2018","unstructured":"Leslie Hwang, Beomjin Kwon, and Martin Wong. 2018. Accurate models for optimizing tapered microchannel heat sinks in 3D ICs. In Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI). 58\u201363."},{"key":"e_1_3_2_27_2","first-page":"86","volume-title":"Proceedings of the ISPASS","year":"2013","unstructured":"Nan Jiang, Daniel U. Becker, George Michelogiannakis, James Balfour, Brian Towles, D. E. Shaw, John Kim, and William J. Dally. 2013. A detailed and flexible cycle-accurate network-on-chip simulator. In Proceedings of the ISPASS. IEEE, 86\u201396."},{"issue":"3","key":"e_1_3_2_28_2","doi-asserted-by":"crossref","first-page":"536","DOI":"10.1109\/TCAPT.2008.2002554","article-title":"Modeling of cylindrical pin-fin heat sinks for electronic packaging","volume":"31","author":"Khan Waqar Ahmed","year":"2008","unstructured":"Waqar Ahmed Khan, J. Richard Culham, and M. Michael Yovanovich. 2008. Modeling of cylindrical pin-fin heat sinks for electronic packaging. IEEE Transactions on Components and Packaging Technologies 31, 3 (2008), 536\u2013545.","journal-title":"IEEE Transactions on Components and Packaging Technologies"},{"key":"e_1_3_2_29_2","doi-asserted-by":"publisher","DOI":"10.1145\/3476999"},{"key":"e_1_3_2_30_2","first-page":"1","volume-title":"Proceedings of the 2022 IEEE\/ACM ICCAD","year":"2022","unstructured":"Gokul Krishnan, A. Alper Goksoy, Sumit K. Mandal, Zhenyu Wang, Chaitali Chakrabarti, Jae-sun Seo, Umit Y. Ogras, and Yu Cao. 2022. Big-little chiplets for in-memory acceleration of DNNs: A scalable heterogeneous architecture. In Proceedings of the 2022 IEEE\/ACM ICCAD. 1\u20139."},{"key":"e_1_3_2_31_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.icheatmasstransfer.2020.104694"},{"key":"e_1_3_2_32_2","volume-title":"Fundamentals of Heat and Mass Transfer","author":"Bergman Theodore L.","year":"2011","unstructured":"Theodore L. Bergman, Adrienne S. Lavine, Frank P. Incropera, and David P. DeWitt. 2011. Fundamentals of Heat and Mass Transfer. John Wiley and Sons."},{"key":"e_1_3_2_33_2","volume-title":"Chiplet Design and Heterogeneous Integration Packaging","author":"Lau John H.","year":"2023","unstructured":"John H. Lau. 2023. Chiplet Design and Heterogeneous Integration Packaging. Springer."},{"key":"e_1_3_2_34_2","doi-asserted-by":"publisher","DOI":"10.1145\/3508352.3549464"},{"key":"e_1_3_2_35_2","doi-asserted-by":"publisher","DOI":"10.1145\/1089014.1089017"},{"issue":"1","key":"e_1_3_2_36_2","doi-asserted-by":"crossref","first-page":"44","DOI":"10.1109\/TEPM.2009.2037012","article-title":"Ti\/au die backside metallization for flip chip heat spreader attachment","volume":"33","author":"Li Yuquan","year":"2010","unstructured":"Yuquan Li, R. Wayne Johnson, Rui Zhang, Phillip Henson, Patrick Thompson, Tejpal Hooghan, and Jeremias Libres. 2010. Ti\/au die backside metallization for flip chip heat spreader attachment. IEEE Transactions on Electronics Packaging Manufacturing 33, 1 (2010), 44\u201354.","journal-title":"IEEE Transactions on Electronics Packaging Manufacturing"},{"key":"e_1_3_2_37_2","first-page":"991","volume-title":"Proceedings of the DAC","year":"2006","unstructured":"Gian Luca Loi, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Timothy Sherwood, and Kaustav Banerjee. 2006. A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy. In Proceedings of the DAC. 991\u2013996."},{"key":"e_1_3_2_38_2","article-title":"An electrical\u2013thermal co-simulation model of chiplet heterogeneous integration systems","author":"Ma Xiaoning","year":"2024","unstructured":"Xiaoning Ma, Qinzhi Xu, Chenghan Wang, He Cao, Jianyun Liu, Daoqing Zhang, and Zhiqiang Li. 2024. An electrical\u2013thermal co-simulation model of chiplet heterogeneous integration systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 32, 10 (2024), 1769\u20131781.","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"key":"e_1_3_2_39_2","first-page":"1246","volume-title":"Proceedings of the DATE","author":"Ma Yenai","year":"2021","unstructured":"Yenai Ma, Leila Delshadtehrani, Cansu Demirkiran, Jos\u00e9 L. Abellan, and Aiav Joshi. 2021. TAP-2.5 D: A thermally-aware chiplet placement methodology for 2.5 D systems. In Proceedings of the DATE. IEEE, 1246\u20131251."},{"key":"e_1_3_2_40_2","volume-title":"An Introduction to Ansys Fluent 2023","author":"Matsson John E.","year":"2023","unstructured":"John E. Matsson. 2023. An Introduction to Ansys Fluent 2023. Sdc Publications."},{"key":"e_1_3_2_41_2","first-page":"648","volume-title":"Proceedings of the DAC","author":"Meng Jie","year":"2012","unstructured":"Jie Meng, Katsutoshi Kawakami, and Ayse K. Coskun. 2012. Optimizing energy efficiency of 3-D multicore systems with stacked DRAM under power and thermal constraints. In Proceedings of the DAC. 648\u2013655."},{"key":"e_1_3_2_42_2","first-page":"57","volume-title":"Proceedings of the ACM\/IEEE ISCA","year":"2021","unstructured":"Samuel Naffziger, Noah Beck, Thomas Burd, Kevin Lepak, Gabriel H. Loh, Mahesh Subramony, and Sean White. 2021. Pioneering chiplet technology and design for the AMD EPYC\u2122 and Ryzen\u2122 processor families : Industrial product. In Proceedings of the ACM\/IEEE ISCA. 57\u201370."},{"issue":"1","key":"e_1_3_2_43_2","doi-asserted-by":"crossref","first-page":"78","DOI":"10.1109\/6144.991179","article-title":"Characterization of compact heat sink models in natural convection","volume":"25","author":"Narasimhan S.","year":"2002","unstructured":"S. Narasimhan and J. Majdalani. 2002. Characterization of compact heat sink models in natural convection. IEEE Transactions on Components and Packaging Technologies 25, 1 (2002), 78\u201386.","journal-title":"IEEE Transactions on Components and Packaging Technologies"},{"key":"e_1_3_2_44_2","doi-asserted-by":"crossref","DOI":"10.1017\/CBO9780511841606","volume-title":"Heat Transfer","author":"Nellis Gregory","year":"2008","unstructured":"Gregory Nellis and Sanford Klein. 2008. Heat Transfer. Cambridge University Press."},{"key":"e_1_3_2_45_2","first-page":"1","volume-title":"Proceedings of the 2024 IEEE 42nd VLSI Test Symposium (VTS)","author":"Park Jaehyun","year":"2024","unstructured":"Jaehyun Park, Alish Kanani, Lukas Pfromm, Harsh Sharma, Parth Solanki, Eric Tervo, Janardhan Rao Doppa, Partha Pratim Pande, and Umit Y. Ogras. 2024. Thermal modeling and management challenges in heterogenous integration: 2.5 D chiplet platforms and beyond. In Proceedings of the 2024 IEEE 42nd VLSI Test Symposium (VTS). 1\u20134."},{"key":"e_1_3_2_46_2","first-page":"48","volume-title":"Proceedings of the DATE","year":"2019","unstructured":"Sheriff Sadiqbatcha, Hengyang Zhao, Hussam Amrouch, J\u00f6rg Henkel, and Sheldon X.-D. Tan. 2019. Hot spot identification and system parameterized thermal modeling for multi-core processors through infrared thermal imaging. In Proceedings of the DATE. 48\u201353."},{"key":"e_1_3_2_47_2","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2012.2223553"},{"issue":"6","key":"e_1_3_2_48_2","doi-asserted-by":"crossref","first-page":"107","DOI":"10.1145\/3460227","article-title":"Simba: Scaling deep-learning inference with multi-chip-module-based architecture","volume":"64","year":"2021","unstructured":"Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel Emer, C. Thomas Gray, Brucek Khailany, and Stephen W. Keckler. 2021. Simba: Scaling deep-learning inference with multi-chip-module-based architecture. Communications of the ACM 64, 6, 107\u2013116.","journal-title":"Communications of the ACM"},{"issue":"10","key":"e_1_3_2_49_2","first-page":"1586","article-title":"Accurate direct and indirect on-chip temperature sensing for efficient dynamic thermal management","volume":"29","author":"Sharifi Shervin","year":"2010","unstructured":"Shervin Sharifi and Tajana \u0160imuni\u0107 Rosing. 2010. Accurate direct and indirect on-chip temperature sensing for efficient dynamic thermal management. IEEE TCAD-IC 29, 10 (2010), 1586\u20131599.","journal-title":"IEEE TCAD-IC"},{"key":"e_1_3_2_50_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCPMT.2022.3207195"},{"issue":"11","key":"e_1_3_2_51_2","first-page":"4145","article-title":"SWAP: A server-scale communication-aware chiplet-based manycore PIM accelerator","volume":"41","year":"2022","unstructured":"Harsh Sharma, Sumit K. Mandal, Janardhan Rao Doppa, Umit Y. Ogras, and Partha Pratim Pande. 2022. SWAP: A server-scale communication-aware chiplet-based manycore PIM accelerator. IEEE TCAD-IC 41, 11 (2022), 4145\u20134156.","journal-title":"IEEE TCAD-IC"},{"key":"e_1_3_2_52_2","doi-asserted-by":"publisher","DOI":"10.1145\/3608098"},{"key":"e_1_3_2_53_2","doi-asserted-by":"publisher","DOI":"10.1145\/980152.980157"},{"key":"e_1_3_2_54_2","doi-asserted-by":"publisher","DOI":"10.1145\/980152.980157"},{"key":"e_1_3_2_55_2","doi-asserted-by":"crossref","first-page":"876","DOI":"10.1109\/ISCA59077.2024.00068","volume-title":"Proceedings of the 2024 ACM\/IEEE 51st Annual International Symposium on Computer Architecture (ISCA)","author":"Smith Alan","year":"2024","unstructured":"Alan Smith, Gabriel H. Loh, Michael J. Schulte, Mike Ignatowski, Samuel Naffziger, Mike Mantor, Mark Fowler Nathan Kalyanasundharam, Vamsi Alla, Nicholas Malaya, Joseph L. Greathouse, et\u00a0al. 2024. Realizing the AMD exascale heterogeneous processor vision: Industry product. In Proceedings of the 2024 ACM\/IEEE 51st Annual International Symposium on Computer Architecture (ISCA). IEEE, 876\u2013889."},{"key":"e_1_3_2_56_2","first-page":"541","volume-title":"Proceedings of the HPCA","author":"Song Linghao","year":"2017","unstructured":"Linghao Song, Xuehai Qian, Hai Li, and Yiran Chen. 2017. Pipelayer: A pipelined reram-based accelerator for deep learning. In Proceedings of the HPCA. IEEE, 541\u2013552."},{"key":"e_1_3_2_57_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2013.127"},{"key":"e_1_3_2_58_2","doi-asserted-by":"publisher","DOI":"10.1145\/2966986.2980095"},{"issue":"2","key":"e_1_3_2_59_2","first-page":"35","article-title":"A survey of chip-level thermal simulators","volume":"52","author":"Sultan Hameedah","year":"2019","unstructured":"Hameedah Sultan, Anjali Chauhan, and Smruti R. Sarangi. 2019. A survey of chip-level thermal simulators. ACM Computing Surveys 52, 2, Article 42 {2019), 35 pages.","journal-title":"ACM Computing Surveys"},{"key":"e_1_3_2_60_2","first-page":"1","volume-title":"Proceedings of the 2023 60th ACM\/IEEE Design Automation Conference (DAC)","author":"Vanna-Iampikul Pruek","year":"2023","unstructured":"Pruek Vanna-Iampikul, Lingjun Zhu, Serhat Erdogan, Mohanalingam Kathaperumal, Ravi Agarwal, Ram Gupta, Kevin Rinebold, and Sung Kyu Lim. 2023. Glass interposer integration of logic and memory chiplets: PPA and power\/signal integrity benefits. In Proceedings of the 2023 60th ACM\/IEEE Design Automation Conference (DAC). IEEE, 1\u20136."},{"key":"e_1_3_2_61_2","volume-title":"Agilex FPGAs Deliver a Game-Changing Combination of Flexibility and Agility for the Data-Centric World","author":"Won Martin","year":"2023","unstructured":"Martin Won. 2023. Agilex FPGAs Deliver a Game-Changing Combination of Flexibility and Agility for the Data-Centric World. Technical Report. Intel."},{"issue":"9","key":"e_1_3_2_62_2","doi-asserted-by":"crossref","first-page":"1336","DOI":"10.1109\/TCPMT.2011.2155655","article-title":"Fabrication of high aspect ratio TSV and assembly with fine-pitch low-cost solder microbump for Si interposer technology with high-density interconnects","volume":"1","author":"Yu Aibin","year":"2011","unstructured":"Aibin Yu, John H. Lau, Soon Wee Ho, Aditya Kumar, Wai Yin Hnin, Wen Sheng Lee, Ming Ching Jong, Vasarla Nagendra Sekhar, Vaidyanathan Kripesh, Damaruganath Pinjala, et\u00a0al. 2011. Fabrication of high aspect ratio TSV and assembly with fine-pitch low-cost solder microbump for Si interposer technology with high-density interconnects. IEEE Transactions on Components, Packaging and Manufacturing Technology 1, 9 (2011), 1336\u20131344.","journal-title":"IEEE Transactions on Components, Packaging and Manufacturing Technology"},{"issue":"4","key":"e_1_3_2_63_2","first-page":"1048","article-title":"PACT: An extensible parallel thermal simulator for emerging integration and cooling technologies","volume":"41","year":"2021","unstructured":"Zihao Yuan, Prachi Shukla, Sofiane Chetoui, Sean Nemtzow, Sherief Reda, and Ayse K. Coskun. 2021. PACT: An extensible parallel thermal simulator for emerging integration and cooling technologies. IEEE TCAD-IC 41, 4 (2021), 1048\u20131061.","journal-title":"IEEE TCAD-IC"},{"key":"e_1_3_2_64_2","first-page":"1065","volume-title":"Proceedings of the ISCAS","author":"Zanini Francesco","year":"2010","unstructured":"Francesco Zanini, David Atienza, Colin N. Jones, and Giovanni De Micheli. 2010. Temperature sensor placement in thermal management systems for MPSoCs. In Proceedings of the ISCAS. 1065\u20131068."},{"key":"e_1_3_2_65_2","first-page":"1","volume-title":"Proceedings of the IEEE Hot Chips 32 Symposium","author":"Zaruba Florian","year":"2020","unstructured":"Florian Zaruba, Fabian Schuiki, and Luca Benini. 2020. A 4096-core RISC-V chiplet architecture for ultra-efficient floating-point computing. In Proceedings of the IEEE Hot Chips 32 Symposium. IEEE Computer Society, 1\u201324."},{"issue":"5","key":"e_1_3_2_66_2","first-page":"1453","article-title":"Full-chip power density and thermal map characterization for commercial microprocessors under heat sink cooling","volume":"41","year":"2021","unstructured":"Jinwei Zhang, Sheriff Sadiqbatcha, Michael O\u2019Dea, Hussam Amrouch, and Sheldon X.-D. Tan. 2021. Full-chip power density and thermal map characterization for commercial microprocessors under heat sink cooling. IEEE TCAD-IC. 41, 5 (2021), 1453\u20131466.","journal-title":"IEEE TCAD-IC."},{"key":"e_1_3_2_67_2","first-page":"432","volume-title":"Proceedings of the IEEE International Conference on Computer Design","author":"Zhang Yufu","year":"2008","unstructured":"Yufu Zhang, Ankur Srivastava, and Mohamed Zahran. 2008. Chip level thermal profile estimation using on-chip temperature sensors. In Proceedings of the IEEE International Conference on Computer Design. 432\u2013437."},{"issue":"10","key":"e_1_3_2_68_2","first-page":"1973","article-title":"Temperature-aware DRAM cache management\u2014relaxing thermal constraints in 3-D systems","volume":"39","year":"2020","unstructured":"Minxuan Zhou, Andreas Prodromou, Rui Wang, Hailong Yang, Depei Qian, and Dean Tullsen. 2020. Temperature-aware DRAM cache management\u2014relaxing thermal constraints in 3-D systems. IEEE TCAD-IC 39, 10 (2020), 1973\u20131986.","journal-title":"IEEE TCAD-IC"},{"issue":"6","key":"e_1_3_2_69_2","doi-asserted-by":"crossref","first-page":"956","DOI":"10.1109\/TCPMT.2022.3174608","article-title":"Thermal modeling of a chiplet-based packaging with a 2.5-D through-silicon via interposer","volume":"12","author":"Zhou Minghao","year":"2022","unstructured":"Minghao Zhou, Li Li, Fengze Hou, Guoqiang He, and Jiaqi Fan. 2022. Thermal modeling of a chiplet-based packaging with a 2.5-D through-silicon via interposer. IEEE Transactions on Components, Packaging and Manufacturing Technology 12, 6 (2022), 956\u2013963.","journal-title":"IEEE Transactions on Components, Packaging and Manufacturing Technology"}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3765905","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,11,10]],"date-time":"2025-11-10T14:14:17Z","timestamp":1762784057000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3765905"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,11,10]]},"references-count":68,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2026,1,31]]}},"alternative-id":["10.1145\/3765905"],"URL":"https:\/\/doi.org\/10.1145\/3765905","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"value":"1084-4309","type":"print"},{"value":"1557-7309","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,11,10]]},"assertion":[{"value":"2025-02-14","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2025-08-25","order":2,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2025-11-10","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}