{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,6]],"date-time":"2026-01-06T15:07:44Z","timestamp":1767712064915,"version":"3.48.0"},"reference-count":14,"publisher":"Association for Computing Machinery (ACM)","issue":"1","content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2026,1,31]]},"abstract":"<jats:p>In modern automotive system-on-chip (SoC) designs, large embedded flash memories have become a standard feature. Since they occupy a significant percentage of the die area, their impact on the SoCs\u2019 overall yield is substantial, making them a critical component in the production process. Embedded memories are then deeply tested to unsure their reliability. The data collected through these tests are fundamental to chip designers and test engineers to iron out their designs and understand the most common failure mechanisms. A common approach for data collection is the generation of bitmaps based on the gathering of individual fail coordinates in a list-based fashion. Other more efficient compaction or compression approaches exist and all these approaches can use dedicated internal memories to store the result of a given test. Unfortunately, all the methods currently found in the literature do not allow diagnostic data retention along multiple tests, requiring constant and time-consuming communications with the external tester, increasing the test cost for the manufacturers.<\/jats:p>\n                  <jats:p\/>\n                  <jats:p>\n                    This article presents an on-chip algorithm to compact and retain diagnostic information from multi-step embedded memories testing. The foundation of this work lies in an efficient shape recognition and encoding algorithm. The collected information is stored in a dedicated nonvolatile on-chip memory. Information about the tests that generated a given set of fault shapes is also encoded in this dedicated diagnostic memory, enabling manufacturers to collect all the diagnostic information at the end of their test flow. Experimental results on over 110 Automotive SoCs made by Infineon\n                    <jats:sup>TM<\/jats:sup>\n                    show that using the proposed approach, 100% of the diagnostic information of devices undergoing a standard automotive-grade test flow is permanently encodable in a limited 24 KB diagnostic space while also consistently reducing the total test time of up to 53.8% with respect to traditional list-based approaches.\n                  <\/jats:p>","DOI":"10.1145\/3766550","type":"journal-article","created":{"date-parts":[[2025,10,10]],"date-time":"2025-10-10T11:29:36Z","timestamp":1760095776000},"page":"1-15","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["A Versatile Strategy for Comprehensive Data Collection and Retention in Embedded SoC Memories"],"prefix":"10.1145","volume":"25","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-0985-9327","authenticated-orcid":false,"given":"Paolo","family":"Bernardi","sequence":"first","affiliation":[{"name":"Polytechnic of Turin","place":["Torino, Italy"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6316-4123","authenticated-orcid":false,"given":"Giorgio","family":"Insinga","sequence":"additional","affiliation":[{"name":"Polytechnic of Turin","place":["Torino, Italy"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0001-6513-9148","authenticated-orcid":false,"given":"Matteo","family":"Battilana","sequence":"additional","affiliation":[{"name":"Infineon Technologies","place":["Padova, Italy"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0008-8844-3119","authenticated-orcid":false,"given":"Peter","family":"Beer","sequence":"additional","affiliation":[{"name":"Infineon Technologies AG","place":["Neubiberg, Germany"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0000-4329-6540","authenticated-orcid":false,"given":"Giambattista","family":"Carnevale","sequence":"additional","affiliation":[{"name":"Infineon Technologies","place":["Padova, Italy"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0005-8862-7645","authenticated-orcid":false,"given":"Matteo","family":"Coppetta","sequence":"additional","affiliation":[{"name":"Infineon Technologies","place":["Padova, Italy"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0003-9292-6969","authenticated-orcid":false,"given":"Nellina","family":"Mautone","sequence":"additional","affiliation":[{"name":"Infineon Technologies AG","place":["Neubiberg, Germany"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0005-6644-3669","authenticated-orcid":false,"given":"Alberto","family":"Repele","sequence":"additional","affiliation":[{"name":"Infineon Technologies","place":["Padova, Italy"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0007-2619-9248","authenticated-orcid":false,"given":"Pierre","family":"Scaramuzza","sequence":"additional","affiliation":[{"name":"Infineon Technologies","place":["Padova, Italy"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0003-4341-473X","authenticated-orcid":false,"given":"Rudolf","family":"Ullmann","sequence":"additional","affiliation":[{"name":"Infineon Technologies AG","place":["Neubiberg, Germany"]}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2026,1,6]]},"reference":[{"key":"e_1_3_1_2_2","first-page":"214","volume-title":"Proceedings of the Conference on Design, Automation and Test in Europe (DATE\u201910)","author":"Goor Ad van de","year":"2010","unstructured":"Ad van de Goor, Georgi Gaydadjiev, and Said Hamdioui. 2010. Memory testing with a RISC microcontroller. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE\u201910). European Design and Automation Association, Leuven, BEL, 214\u2013219."},{"key":"e_1_3_1_3_2","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.92"},{"key":"e_1_3_1_4_2","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687435"},{"key":"e_1_3_1_5_2","first-page":"521","volume-title":"Proceedings of the Conference on Design, Automation and Test in Europe (DATE\u201912)","author":"Cai Yu","year":"2012","unstructured":"Yu Cai, Erich F. Haratsch, Onur Mutlu, and Ken Mai. 2012. Error patterns in MLC NAND flash memory: Measurement, characterization, and analysis. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE\u201912). EDA Consortium, San Jose, CA, USA, 521\u2013526."},{"key":"e_1_3_1_6_2","doi-asserted-by":"publisher","DOI":"10.1145\/1964144.1964146"},{"key":"e_1_3_1_7_2","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS56730.2022.9897647"},{"key":"e_1_3_1_8_2","doi-asserted-by":"publisher","DOI":"10.1109\/ETS56758.2023.10174126"},{"key":"e_1_3_1_9_2","doi-asserted-by":"publisher","DOI":"10.1109\/ETS54262.2022.9810445"},{"key":"e_1_3_1_10_2","article-title":"A survey on the architecture for an efficient memory built in self-test for configurable embedded SRAM memory","volume":"2","author":"Nisha Omanakuttan Sheela","year":"2015","unstructured":"Omanakuttan Sheela Nisha and Dr.K. Siva Sankar. 2015. A survey on the architecture for an efficient memory built in self-test for configurable embedded SRAM memory. Int. J. Mod. Trends Eng. Res. 2, 3 (2015). Retrieved from https:\/\/api.semanticscholar.org\/CorpusID:26875254","journal-title":"Int. J. Mod. Trends Eng. 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