{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,30]],"date-time":"2026-01-30T17:27:42Z","timestamp":1769794062189,"version":"3.49.0"},"publisher-location":"New York, NY, USA","reference-count":40,"publisher":"ACM","license":[{"start":{"date-parts":[[2027,1,29]],"date-time":"2027-01-29T00:00:00Z","timestamp":1801180800000},"content-version":"vor","delay-in-days":480,"URL":"http:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000001","name":"NSF (National Science Foundation)","doi-asserted-by":"publisher","award":["CCF-2312508"],"award-info":[{"award-number":["CCF-2312508"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"NSF (National Science Foundation)","doi-asserted-by":"publisher","award":["CCF-2210754"],"award-info":[{"award-number":["CCF-2210754"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2025,10,6]]},"DOI":"10.1145\/3767110.3767125","type":"proceedings-article","created":{"date-parts":[[2026,1,30]],"date-time":"2026-01-30T04:36:01Z","timestamp":1769747761000},"page":"15-27","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["ZipCXL: CXL-based Main Memory Compression at Low Performance Penalty"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0009-0003-7975-0102","authenticated-orcid":false,"family":"Asad Ul Haq","sequence":"first","affiliation":[{"name":"ECSE, Rensselaer Polytechnic Institute, Troy, NY, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3177-5071","authenticated-orcid":false,"given":"Rui","family":"Xie","sequence":"additional","affiliation":[{"name":"ECSE, Rensselaer Polytechnic Institute, Troy, NY, USA"}]},{"ORCID":"https:\/\/orcid.org\/0009-0000-8535-7911","authenticated-orcid":false,"given":"Linsen","family":"Ma","sequence":"additional","affiliation":[{"name":"ECSE, Rensselaer Polytechnic Institute, Troy, NY, USA"}]},{"ORCID":"https:\/\/orcid.org\/0009-0009-4718-8825","authenticated-orcid":false,"given":"Yunhua","family":"Fang","sequence":"additional","affiliation":[{"name":"ECSE, Rensselaer Polytechnic Institute, Troy, NY, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0792-8146","authenticated-orcid":false,"given":"Liu","family":"Liu","sequence":"additional","affiliation":[{"name":"Rensselaer Polytechnic Institute, Troy, NY, USA"}]},{"ORCID":"https:\/\/orcid.org\/0009-0009-8005-0043","authenticated-orcid":false,"given":"Tong","family":"Zhang","sequence":"additional","affiliation":[{"name":"Rensselaer Polytechnic Institute, Troy, NY, USA"}]}],"member":"320","published-online":{"date-parts":[[2026,1,29]]},"reference":[{"key":"e_1_3_3_2_2_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA45697.2020.00012"},{"key":"e_1_3_3_2_3_2","unstructured":"Alaa\u00a0R Alameldeen and David\u00a0A. Wood. 2004. Frequent Pattern Compression: A Significance-Based Compression Scheme for L2 Caches. Technical Report Computer Sciences Dept. UW-Madison (2004)."},{"key":"e_1_3_3_2_4_2","volume-title":"Opensource datasets from Amazon AWS","year":"2025","unstructured":"Amazon. 2025. Opensource datasets from Amazon AWS. https:\/\/registry.opendata.aws\/Retrieved February 15, 2025 from"},{"key":"e_1_3_3_2_5_2","volume-title":"45nm free PDK","author":"State\u00a0University Electronic Design\u00a0Automation at North Carolina","year":"2025","unstructured":"Electronic Design\u00a0Automation at North Carolina State\u00a0University. 2025. 45nm free PDK. https:\/\/eda.ncsu.edu\/freepdk\/freepdk45\/Retrieved February 15, 2025 from"},{"key":"e_1_3_3_2_6_2","doi-asserted-by":"crossref","unstructured":"Yann Collet. 2021. RFC 8878: Zstandard Compression and the \u2018application\/zstd\u2019 Media Type.","DOI":"10.17487\/RFC8878"},{"key":"e_1_3_3_2_7_2","volume-title":"SPEC CPU\u00ae benchmark","author":"Corporation Standard Performance\u00a0Evaluation","year":"2006","unstructured":"Standard Performance\u00a0Evaluation Corporation. 2006. SPEC CPU\u00ae benchmark. https:\/\/www.spec.org\/cpu2006\/"},{"key":"e_1_3_3_2_8_2","doi-asserted-by":"crossref","unstructured":"David\u00a0J Craft. 1998. A fast hardware data compression algorithm and some algorithmic extensions. IBM Journal of Research and Development 42 6 (1998) 733\u2013746.","DOI":"10.1147\/rd.426.0733"},{"key":"e_1_3_3_2_9_2","doi-asserted-by":"crossref","unstructured":"Debendra Das\u00a0Sharma Robert Blankenship and Daniel Berger. 2024. An Introduction to the Compute Express Link (CXL) Interconnect. Comput. Surveys 56 11 (2024) 1\u201337.","DOI":"10.1145\/3669900"},{"key":"e_1_3_3_2_10_2","unstructured":"Sebastian Deorowicz. 2014. Silesia compression corpus. Silesia University (2014). https:\/\/sun.aei.polsl.pl\/\/\u00a0sdeor\/index.php?page=silesia"},{"key":"e_1_3_3_2_11_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.6"},{"key":"e_1_3_3_2_12_2","unstructured":"Michael\u00a0J. Freedman. 2000. The Compression Cache: Virtual Memory Compression for Handheld Computers. https:\/\/api.semanticscholar.org\/CorpusID:59821443"},{"key":"e_1_3_3_2_13_2","unstructured":"Jean-Loup Gailly and Mark Adler. 2004. Zlib compression library. Apollo - University of Cambridge Repository (2004)."},{"key":"e_1_3_3_2_14_2","doi-asserted-by":"publisher","DOI":"10.48550\/arXiv.2210.14324"},{"key":"e_1_3_3_2_15_2","doi-asserted-by":"crossref","unstructured":"David\u00a0A Huffman. 1952. A method for the construction of minimum-redundancy codes. Proceedings of the IRE 40 9 (1952) 1098\u20131101.","DOI":"10.1109\/JRPROC.1952.273898"},{"key":"e_1_3_3_2_16_2","volume-title":"CXL Near-Memory Compute and Expansion","author":"Inc. Marvell\u00a0Technology","year":"2025","unstructured":"Marvell\u00a0Technology Inc.2025. CXL Near-Memory Compute and Expansion. Retrieved February 15, 2025 from https:\/\/www.marvell.com\/products\/cxl.html"},{"key":"e_1_3_3_2_17_2","volume-title":"Open Datasets from Kaggle","year":"2025","unstructured":"Kaggle. 2025. Open Datasets from Kaggle. https:\/\/www.kaggle.com\/datasetsRetrieved February 15, 2025 from"},{"key":"e_1_3_3_2_18_2","doi-asserted-by":"crossref","unstructured":"Jungrae Kim Michael Sullivan Esha Choukse and Mattan Erez. 2016. Bit-plane compression: Transforming data for better compression in many-core architectures. ACM SIGARCH Computer Architecture News 44 3 (2016) 329\u2013340.","DOI":"10.1145\/3007787.3001172"},{"key":"e_1_3_3_2_19_2","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2017.12"},{"key":"e_1_3_3_2_20_2","doi-asserted-by":"publisher","DOI":"10.1145\/3575693.3578835"},{"key":"e_1_3_3_2_21_2","doi-asserted-by":"crossref","unstructured":"Shang Li Zhiyuan Yang Dhiraj Reddy Ankur Srivastava and Bruce Jacob. 2020. DRAMsim3: A cycle-accurate thermal-capable DRAM simulator. IEEE Computer Architecture Letters 19 2 (2020) 106\u2013109.","DOI":"10.1109\/LCA.2020.2973991"},{"key":"e_1_3_3_2_22_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA56546.2023.10071115"},{"key":"e_1_3_3_2_23_2","volume-title":"Just How Bad Is CXL Memory Latency?","author":"Mann Tobias","year":"2022","unstructured":"Tobias Mann. 2022. Just How Bad Is CXL Memory Latency?Retrieved February 15, 2025 from https:\/\/www.nextplatform.com\/2022\/12\/05\/just-how-bad-is-cxl-memory-latency\/"},{"key":"e_1_3_3_2_24_2","volume-title":"Micron memory expansion module using CXL","author":"Inc. Micron Technology,","year":"2023","unstructured":"Micron Technology, Inc.2023. Micron memory expansion module using CXL. https:\/\/www.micron.com\/products\/memory\/cxl-memoryRetrieved February 15, 2025 from"},{"key":"e_1_3_3_2_25_2","volume-title":"Making Memories at HyperScale with CXL","author":"Morris Brian","year":"2024","unstructured":"Brian Morris and Prakash Chauhan. 2024. Making Memories at HyperScale with CXL. https:\/\/computeexpresslink.org\/wp-content\/uploads\/2024\/10\/CXL_Q3-Webinar_Making-Memories-at-HyperScale-with-CXL_FINAL.pdfRetrieved February 15, 2025 from"},{"key":"e_1_3_3_2_26_2","doi-asserted-by":"publisher","DOI":"10.1109\/IDAACS.2001.941979"},{"key":"e_1_3_3_2_27_2","doi-asserted-by":"crossref","unstructured":"Keshab\u00a0K Parhi. 1992. High-speed VLSI architectures for Huffman and Viterbi decoders. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 39 6 (1992) 385\u2013391.","DOI":"10.1109\/82.145297"},{"key":"e_1_3_3_2_28_2","volume-title":"VLSI digital signal processing systems: design and implementation","author":"Parhi Keshab\u00a0K","year":"2007","unstructured":"Keshab\u00a0K Parhi. 2007. VLSI digital signal processing systems: design and implementation. John Wiley & Sons."},{"key":"e_1_3_3_2_29_2","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540724"},{"key":"e_1_3_3_2_30_2","doi-asserted-by":"publisher","DOI":"10.1145\/2370816.2370870"},{"key":"e_1_3_3_2_31_2","volume-title":"Quantative dataset source from Quandl","year":"2025","unstructured":"Quandl. 2025. Quantative dataset source from Quandl. https:\/\/data.nasdaq.com\/publishers\/QDLRetrieved February 15, 2025 from"},{"key":"e_1_3_3_2_32_2","volume-title":"Samsung CXL memory solutions","author":"Ltd. Samsung Electronics Co.,","year":"2024","unstructured":"Samsung Electronics Co., Ltd.2024. Samsung CXL memory solutions. https:\/\/semiconductor.samsung.com\/us\/news-events\/tech-blog\/samsung-cxl-solutions-cmm-h\/Retrieved February 15, 2025 from"},{"key":"e_1_3_3_2_33_2","doi-asserted-by":"publisher","DOI":"10.5555\/AAI29393720"},{"key":"e_1_3_3_2_34_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835972"},{"key":"e_1_3_3_2_35_2","doi-asserted-by":"publisher","DOI":"10.1145\/2442516.2442530"},{"key":"e_1_3_3_2_36_2","volume-title":"SK Hynix Presents CXL Memory Solutions Set to Power the AI Era at CXL DevCon 2024","author":"Inc. SK Hynix","year":"2024","unstructured":"SK Hynix Inc.2024. SK Hynix Presents CXL Memory Solutions Set to Power the AI Era at CXL DevCon 2024. https:\/\/news.skhynix.com\/sk-hynix-presents-ai-memory-solutions-at-cxl-devcon-2024\/Retrieved February 15, 2025 from"},{"key":"e_1_3_3_2_37_2","volume-title":"Synopsys Design Compiler Webpage","author":"Inc. Synopsys,","year":"2025","unstructured":"Synopsys, Inc.2025. Synopsys Design Compiler Webpage. https:\/\/www.synopsys.com\/implementation-and-signoff\/rtl-synthesis-test\/dc-ultra.htmlRetrieved February 15, 2025 from"},{"key":"e_1_3_3_2_38_2","volume-title":"TPC-H benchmark","author":"(TPC) Transaction Processing Performance\u00a0Council","year":"2025","unstructured":"Transaction Processing Performance\u00a0Council (TPC). 2025. TPC-H benchmark. https:\/\/www.tpc.org\/tpch\/Retrieved February 15, 2025 from"},{"key":"e_1_3_3_2_39_2","doi-asserted-by":"crossref","unstructured":"R\u00a0Brett Tremaine Peter\u00a0A Franaszek John\u00a0T Robinson Charles\u00a0O Schulz T\u00a0Basil Smith Michael\u00a0E Wazlowski and P\u00a0Maurice Bland. 2001. IBM memory expansion technology (MXT). IBM Journal of Research and Development 45 2 (2001) 271\u2013285.","DOI":"10.1147\/rd.452.0271"},{"key":"e_1_3_3_2_40_2","doi-asserted-by":"crossref","unstructured":"Jacob Ziv and Abraham Lempel. 1977. A universal algorithm for sequential data compression. IEEE Transactions on information theory 23 3 (1977) 337\u2013343.","DOI":"10.1109\/TIT.1977.1055714"},{"key":"e_1_3_3_2_41_2","doi-asserted-by":"publisher","DOI":"10.1145\/3357526.3357558"}],"event":{"name":"MemSys '25: International Symposium on Memory Systems","location":"Washington USA","acronym":"MemSys '25"},"container-title":["Proceedings of the International Symposium on Memory Systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3767110.3767125","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3767110.3767125","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,1,30]],"date-time":"2026-01-30T04:36:06Z","timestamp":1769747766000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3767110.3767125"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,10,6]]},"references-count":40,"alternative-id":["10.1145\/3767110.3767125","10.1145\/3767110"],"URL":"https:\/\/doi.org\/10.1145\/3767110.3767125","relation":{},"subject":[],"published":{"date-parts":[[2025,10,6]]},"assertion":[{"value":"2026-01-29","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}