{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,26]],"date-time":"2026-03-26T12:23:53Z","timestamp":1774527833107,"version":"3.50.1"},"reference-count":95,"publisher":"Association for Computing Machinery (ACM)","issue":"2","funder":[{"DOI":"10.13039\/501100012166","name":"National Key R&D Program of China","doi-asserted-by":"crossref","award":["2024YFB4505201"],"award-info":[{"award-number":["2024YFB4505201"]}],"id":[{"id":"10.13039\/501100012166","id-type":"DOI","asserted-by":"crossref"}]},{"name":"Major Research Plan of the National Natural Science Foundation of China","award":["92373114"],"award-info":[{"award-number":["92373114"]}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"crossref","award":["No. U22B2023, No. 62441220 and No. 624B2120"],"award-info":[{"award-number":["No. U22B2023, No. 62441220 and No. 624B2120"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"crossref"}]},{"name":"Xiaomi Young Scholars"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Storage"],"published-print":{"date-parts":[[2026,5,31]]},"abstract":"<jats:p>\n                    <jats:italic toggle=\"yes\">High-bandwidth memory<\/jats:italic>\n                    (HBM) is regarded as a promising technology for fundamentally overcoming the memory wall. It stacks up multiple DRAM dies vertically to dramatically improve the memory access bandwidth. However, this architecture also comes with more severe reliability issues, since HBM not only inherits error patterns of the conventional DRAM, but also introduces new error causes.\n                  <\/jats:p>\n                  <jats:p>\n                    In this article, we conduct the first systematical study on HBM errors, which cover over 460 million error events collected from 19 data centers and span over two years of deployment under a variety of services. Through error analyses and methodology validations, we confirm that the HBM exhibits different error patterns from conventional DRAM, in terms of spatial locality, temporal correlation, and sensor metrics which make empirical prediction models for DRAM error prediction ineffective for HBM. We design and implement\n                    <jats:sans-serif>Calchas<\/jats:sans-serif>\n                    , a hierarchical failure prediction framework for HBM based on our findings, which integrate spatial, temporal, and sensor information from various device levels to predict upcoming failures. The results demonstrate the feasibility of failure prediction across hierarchical levels.\n                  <\/jats:p>","DOI":"10.1145\/3767333","type":"journal-article","created":{"date-parts":[[2025,9,12]],"date-time":"2025-09-12T11:49:11Z","timestamp":1757677751000},"page":"1-34","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Looking Back to Move Forward: Unveiling the Mysteries of HBM Errors to Predict Future Failures"],"prefix":"10.1145","volume":"22","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-2355-3738","authenticated-orcid":false,"given":"Shuyue","family":"Zhou","sequence":"first","affiliation":[{"name":"School of Informatics, Xiamen University","place":["Xiamen, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0007-6042-8323","authenticated-orcid":false,"given":"Xinbin","family":"Hu","sequence":"additional","affiliation":[{"name":"School of Informatics, Xiamen University","place":["Xiamen, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0001-9008-5401","authenticated-orcid":false,"given":"Ronglong","family":"Wu","sequence":"additional","affiliation":[{"name":"School of Informatics, Xiamen University","place":["Xiamen, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0003-3790-6519","authenticated-orcid":false,"given":"Jiahao","family":"Lu","sequence":"additional","affiliation":[{"name":"School of Informatics, Xiamen University","place":["Xiamen, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2673-5868","authenticated-orcid":false,"given":"Zhirong","family":"Shen","sequence":"additional","affiliation":[{"name":"School of Informatics, Xiamen University","place":["Xiamen, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0002-7346-5418","authenticated-orcid":false,"given":"Zikang","family":"Xu","sequence":"additional","affiliation":[{"name":"School of Informatics, Xiamen University","place":["Xiamen, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9865-2212","authenticated-orcid":false,"given":"Yue","family":"Yu","sequence":"additional","affiliation":[{"name":"Peng Cheng Laboratory","place":["Shenzhen, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0002-5602-3677","authenticated-orcid":false,"given":"Yuze","family":"Jiang","sequence":"additional","affiliation":[{"name":"Department of Statistics, University of Michigan","place":["Ann Arbor, United States"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7362-2789","authenticated-orcid":false,"given":"Jiwu","family":"Shu","sequence":"additional","affiliation":[{"name":"Tsinghua University, Xiamen University","place":["Xiamen, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9179-7363","authenticated-orcid":false,"given":"Kunlin","family":"Yang","sequence":"additional","affiliation":[{"name":"Huawei Technologies Co Ltd","place":["Shenzhen, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0003-7988-109X","authenticated-orcid":false,"given":"Feilong","family":"Lin","sequence":"additional","affiliation":[{"name":"Huawei Technologies Co Ltd","place":["Shenzhen, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6450-8485","authenticated-orcid":false,"given":"Yiming","family":"Zhang","sequence":"additional","affiliation":[{"name":"School of Informatics, Xiamen University","place":["Xiamen, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2026,3,26]]},"reference":[{"key":"e_1_3_2_2_2","unstructured":"2020. NVIDIA A100 Tensor Core GPU. (2020). Retrieved December 1 2023 from https:\/\/www.nvidia.com\/content\/dam\/en-zz\/Solutions\/Data-Center\/a100\/pdf\/a100-80gb-datasheet-update-nvidia-us-1521051-r2-web.pdf"},{"issue":"2","key":"e_1_3_2_3_2","doi-asserted-by":"crossref","first-page":"212","DOI":"10.1145\/1028176.1006719","article-title":"Adaptive cache compression for high-performance processors","volume":"32","author":"Alameldeen Alaa R.","year":"2004","unstructured":"Alaa R. Alameldeen and David A. Wood. 2004. Adaptive cache compression for high-performance processors. ACM SIGARCH Computer Architecture News 32, 2 (2004), 212.","journal-title":"ACM SIGARCH Computer Architecture News"},{"key":"e_1_3_2_4_2","unstructured":"AMD. 2020. AMD RADEON INSTINCT\u2122MI50. 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In Proceeding of the 2020 International SoC Design Conference (ISOCC)."},{"key":"e_1_3_2_7_2","volume-title":"Proceedings of 2016 46th Annual IEEE\/IFIP International Conference on Dependable Systems and Networks Workshop (DSN-W)","author":"Baseman Elisabeth","year":"2016","unstructured":"Elisabeth Baseman, Nathan DeBardeleben, Kurt Ferreira, Scott Levy, Steven Raasch, Vilas Sridharan, Taniya Siddiqua, and Qiang Guan. 2016. Improving DRAM fault characterization through machine learning. In Proceedings of 2016 46th Annual IEEE\/IFIP International Conference on Dependable Systems and Networks Workshop (DSN-W)."},{"key":"e_1_3_2_8_2","volume-title":"Proceedings of 2017 47th Annual IEEE\/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)","author":"Baseman Elisabeth","year":"2017","unstructured":"Elisabeth Baseman, Nathan Debardeleben, Kurt Ferreira, Vilas Sridharan, Taniya Siddiqua, and Olena Tkachenko. 2017. Automating DRAM fault mitigation by learning from experience. In Proceedings of 2017 47th Annual IEEE\/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)."},{"key":"e_1_3_2_9_2","volume-title":"Proceedings of 2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)","author":"Beigi Majed Valad","year":"2023","unstructured":"Majed Valad Beigi, Yi Cao, Sudhanva Gurumurthi, Charles Recchia, Andrew Walton, and Vilas Sridharan. 2023. A systematic study of DDR4 DRAM faults in the field. In Proceedings of 2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)."},{"key":"e_1_3_2_10_2","volume-title":"Proceedings of the 52nd Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO)","author":"Bera Rahul","year":"2019","unstructured":"Rahul Bera, Anant V. Nori, Onur Mutlu, and Sreenivas Subramoney. 2019. Dspatch: Dual spatial pattern prefetcher. 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IEEE Transactions on Information Theory 32, 2 (1986), 181\u2013185.","journal-title":"IEEE Transactions on Information Theory"},{"issue":"8","key":"e_1_3_2_15_2","doi-asserted-by":"crossref","first-page":"1196","DOI":"10.1109\/TVLSI.2009.2020989","article-title":"C-pack: A high-performance microprocessor cache compression algorithm","volume":"18","author":"Chen Xi","year":"2009","unstructured":"Xi Chen, Lei Yang, Robert P. Dick, Li Shang, and Haris Lekatsas. 2009. C-pack: A high-performance microprocessor cache compression algorithm. IEEE Transactions on Very Large Scale Integration Systems 18, 8 (2009), 1196\u20131208.","journal-title":"IEEE Transactions on Very Large Scale Integration Systems"},{"key":"e_1_3_2_16_2","volume-title":"Proceedings of the 2022 41st International Symposium on Reliable Distributed Systems (SRDS)","author":"Cheng Zhinan","year":"2022","unstructured":"Zhinan Cheng, Shujie Han, Patrick P. C. Lee, Xin Li, Jiongzhou Liu, and Zhan Li. 2022. An in-depth correlative study between DRAM errors and server failures in production data centers. In Proceedings of the 2022 41st International Symposium on Reliable Distributed Systems (SRDS)."},{"key":"e_1_3_2_17_2","volume-title":"Proceedings of the 52nd Annual Design Automation Conference (DAC)","author":"Cho Hyungmin","year":"2015","unstructured":"Hyungmin Cho, Chen-Yong Cher, Thomas Shepherd, and Subhasish Mitra. 2015. Understanding soft errors in uncore components. In Proceedings of the 52nd Annual Design Automation Conference (DAC)."},{"key":"e_1_3_2_18_2","unstructured":"kyu Young-Choi Yuze Chi Jie Wang Licheng Guo and Jason Cong. 2020. When HLS meets FPGA HBM: Benchmarking and bandwidth optimization. Retrieved from https:\/\/arxiv.org\/abs\/2010.06075"},{"key":"e_1_3_2_19_2","volume-title":"Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis (SC)","author":"Costa Carlos H. A.","year":"2014","unstructured":"Carlos H. A. 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In Proceedings of the IEEE 39th International Conference on Computer Design (ICCD)."},{"key":"e_1_3_2_25_2","volume-title":"Proceedings of 2020 16th European Dependable Computing Conference (EDCC)","author":"Du Xiaoming","year":"2020","unstructured":"Xiaoming Du, Cong Li, Shen Zhou, Mao Ye, and Jing Li. 2020. Predicting uncorrectable memory errors for proactive replacement: An empirical study on large-scale field data. In Proceedings of 2020 16th European Dependable Computing Conference (EDCC)."},{"key":"e_1_3_2_26_2","volume-title":"Proceedings of the 6th International Conference on Hot Topics in System Dependability (HotDep)","author":"Du Yuyang","year":"2010","unstructured":"Yuyang Du, Hongliang Yu, Yunhong Jiang, Yaozu Dong, and Weimin Zheng. 2010. A rising tide lifts all boats: How memory error prediction and prevention can help with virtualized system longevity. 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Cosmic rays don\u2019t strike twice: Understanding the nature of DRAM errors and the implications for system design. ACM SIGPLAN Notices 47, 4 (2012), 111\u2013122.","journal-title":"ACM SIGPLAN Notices"},{"key":"e_1_3_2_37_2","unstructured":"Intel. 2023. Intel\u00aeStratix\u00ae10. (2023). Retrieved October 1 2023 from https:\/\/www.intel.com\/content\/www\/us\/en\/docs\/programmable\/683189\/21-3-19-6-1\/hbm2-in-intel-stratix-10-devices.html"},{"key":"e_1_3_2_38_2","volume-title":"Proceedings of the 2012 Symposium on VLSI Technology (VLSIT)","author":"Jeddeloh Joe","year":"2012","unstructured":"Joe Jeddeloh and Brent Keeth. 2012. Hybrid memory cube new DRAM architecture increases density and performance. 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Temperature estimation of HBM2 channels with tail distribution of retention errors in FPGA-HBM2 platform. Electronics 12, 1 (2022), 32.","journal-title":"Electronics"},{"key":"e_1_3_2_47_2","volume-title":"Proceedings of the 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)","author":"Larimi Seyed Saber Nabavi","year":"2021","unstructured":"Seyed Saber Nabavi Larimi, Behzad Salami, Osman S. Unsal, Adri\u00e1n Cristal Kestelman, Hamid Sarbazi-Azad, and Onur Mutlu. 2021. Understanding power consumption and reliability of high-bandwidth memory with voltage underscaling. In Proceedings of the 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)."},{"key":"e_1_3_2_48_2","volume-title":"Proceedings of the 2014 Symposium on VLSI Technology: Digest of Technical Papers (VLSIT)","author":"Lee Chang Yeol","year":"2014","unstructured":"Chang Yeol Lee, Sungchul Kim, Hongshin Jun, Kyung Whan Kim, and Sung Joo Hong. 2014. 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In Proceedings of the 2022 52nd Annual IEEE\/IFIP International Conference on Dependable Systems and Networks (DSN)."}],"container-title":["ACM Transactions on Storage"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3767333","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,3,26]],"date-time":"2026-03-26T11:35:30Z","timestamp":1774524930000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3767333"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,3,26]]},"references-count":95,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2026,5,31]]}},"alternative-id":["10.1145\/3767333"],"URL":"https:\/\/doi.org\/10.1145\/3767333","relation":{},"ISSN":["1553-3077","1553-3093"],"issn-type":[{"value":"1553-3077","type":"print"},{"value":"1553-3093","type":"electronic"}],"subject":[],"published":{"date-parts":[[2026,3,26]]},"assertion":[{"value":"2025-02-02","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2025-07-15","order":2,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2026-03-26","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}