{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,19]],"date-time":"2026-03-19T14:51:15Z","timestamp":1773931875286,"version":"3.50.1"},"reference-count":38,"publisher":"Association for Computing Machinery (ACM)","issue":"4","funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"crossref","award":["62474038, and 62274034"],"award-info":[{"award-number":["62474038, and 62274034"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"crossref"}]},{"name":"Key Research and Development Program of Jiangsu Province","award":["BE2023003-2"],"award-info":[{"award-number":["BE2023003-2"]}]},{"DOI":"10.13039\/501100004608","name":"Natural Science Foundation of Jiangsu Province","doi-asserted-by":"crossref","award":["BK20232005"],"award-info":[{"award-number":["BK20232005"]}],"id":[{"id":"10.13039\/501100004608","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/501100012226","name":"Fundamental Research Funds for the Central Universities","doi-asserted-by":"crossref","id":[{"id":"10.13039\/501100012226","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2026,7,31]]},"abstract":"<jats:p>With technology scaling progressing well into deep nanometer region, the number of technology corners surges from dozens to hundreds. This dramatic increase in corners significantly complicates timing closure during Engineering Change Orders (ECO) stages, as performing full-corner static timing analysis (STA) becomes increasingly time-consuming and challenging. Existing methodologies often leverage machine learning (ML) techniques to predict unknown corners based on a subset of known corners. However, as the total number of corners expands, these methods not only require a larger set of known corners but also become highly sensitive to known corner selection. Additionally, as designers push designs into near-threshold voltage regions to enhance energy efficiency, the number of corners increases and the nonlinearity between corners becomes more pronounced. This intensifies the difficulty for current ML-based methods to accurately predict full-corner timing metrics. In this work, we propose FACT, a fast and accurate multi-corner predictor for timing closure optimization. Our approach simplifies the process by necessitating timing analysis under only one known corner. By effectively capturing correlations across diverse technology files, FACT robustly infers full-corner timing metrics, even under challenging near-threshold conditions. Moreover, our framework seamlessly integrates with commercial EDA design flows, making it practical in industrial environments. Experimental results on open-source designs indicate the superior stability of our method, coupled with a significant runtime speed-up over both traditional and prior ML-based timing ECO flows.<\/jats:p>","DOI":"10.1145\/3768166","type":"journal-article","created":{"date-parts":[[2025,9,15]],"date-time":"2025-09-15T11:40:34Z","timestamp":1757936434000},"page":"1-33","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["FACT: Fast and Accurate Multi-Corner Predictor for Timing Closure in Commercial EDA Flows"],"prefix":"10.1145","volume":"31","author":[{"ORCID":"https:\/\/orcid.org\/0009-0009-0926-7856","authenticated-orcid":false,"given":"jiajie","family":"xu","sequence":"first","affiliation":[{"name":"National ASIC research center, Southeast University","place":["Nanjing, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0001-3679-9083","authenticated-orcid":false,"given":"Ziyue","family":"Han","sequence":"additional","affiliation":[{"name":"National ASIC research center, Southeast University","place":["Nanjing, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0004-3534-7343","authenticated-orcid":false,"given":"Shiyang","family":"Wu","sequence":"additional","affiliation":[{"name":"National ASIC research center, Southeast University","place":["Nanjing, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0001-2101-8133","authenticated-orcid":false,"given":"Jiaqi","family":"Gao","sequence":"additional","affiliation":[{"name":"National ASIC research center, Southeast University","place":["Nanjing, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5312-4483","authenticated-orcid":false,"given":"Hao","family":"Yan","sequence":"additional","affiliation":[{"name":"Electrical Engineering, Southeast University","place":["Nanjing, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0629-7154","authenticated-orcid":false,"given":"Longxing","family":"Shi","sequence":"additional","affiliation":[{"name":"Electrical Engineering, Southeast University","place":["Nanjing, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2026,3,19]]},"reference":[{"key":"e_1_3_1_2_2","doi-asserted-by":"publisher","DOI":"10.1007\/s11277-023-10789-3"},{"key":"e_1_3_1_3_2","first-page":"1","volume-title":"2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)","author":"Jin Leilei","year":"2023","unstructured":"Leilei Jin, Jiajie Xu, Wenjie Fu, Hao Yan, Xiao Shi, Ming Ling, and Longxing Shi. 2023. A novel delay calibration method considering interaction between cells and wires. In 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 1\u20136."},{"key":"e_1_3_1_4_2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2647853"},{"key":"e_1_3_1_5_2","first-page":"1","volume-title":"2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)","author":"Xu Jiajie","year":"2024","unstructured":"Jiajie Xu, Leilei Jin, Wenjie Fu, and Longxing Shi. 2024. A deep-learning-based statistical timing prediction method for sub-16nm technologies. In 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 1\u20136."},{"key":"e_1_3_1_6_2","doi-asserted-by":"publisher","DOI":"10.1145\/1233501.1233545"},{"key":"e_1_3_1_7_2","first-page":"1","volume-title":"2007 Design, Automation & Test in Europe Conference & Exhibition","author":"Silva Luis Guerra e","year":"2007","unstructured":"Luis Guerra e Silva, L Miguel Silveira, and Joel R Phillips. 2007. Efficient computation of the worst-delay corner. In 2007 Design, Automation & Test in Europe Conference & Exhibition. IEEE, 1\u20136."},{"key":"e_1_3_1_8_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2023.3286261"},{"key":"e_1_3_1_9_2","first-page":"1","volume-title":"2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)","author":"Zuo Yunfan","year":"2024","unstructured":"Yunfan Zuo, Yuyang Ye, Hongchao Zhang, Tinghuan Chen, Hao Yan, and Longxing Shi. 2024. A graph-learning-driven prediction method for combined electromigration and thermomigration stress on multi-segment interconnects. In 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 1\u20136."},{"key":"e_1_3_1_10_2","article-title":"Enhanced TransUNet framework for predicting static IR drop and chip routability","author":"Zuo Yunfan","year":"2025","unstructured":"Yunfan Zuo, Pinquan Li, Yuwei Sun, Hao Yan, and Longxing Shi. 2025. Enhanced TransUNet framework for predicting static IR drop and chip routability. ACM Transactions on Design Automation of Electronic Systems (2025).","journal-title":"ACM Transactions on Design Automation of Electronic Systems"},{"key":"e_1_3_1_11_2","first-page":"364","volume-title":"2025 International Symposium of Electronics Design Automation (ISEDA)","author":"Han Ziyue","year":"2025","unstructured":"Ziyue Han, Jiajie Xu, and Hao Yan. 2025. Automatic parameter tuning system under multi-threading nondeterminism. In 2025 International Symposium of Electronics Design Automation (ISEDA). IEEE, 364\u2013368."},{"key":"e_1_3_1_12_2","doi-asserted-by":"crossref","first-page":"168","DOI":"10.23919\/DATE.2019.8715102","volume-title":"2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)","author":"Kahng Andrew B","year":"2019","unstructured":"Andrew B Kahng, Uday Mallappa, Lawrence Saul, and Shangyuan Tong. 2019. \u201dUnobserved corner\u201d prediction: Reducing timing analysis effort for faster design convergence in advanced-node design. In 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 168\u2013173."},{"key":"e_1_3_1_13_2","doi-asserted-by":"publisher","DOI":"10.3390\/electronics11101571"},{"key":"e_1_3_1_14_2","doi-asserted-by":"crossref","DOI":"10.1109\/TCAD.2024.3361401","article-title":"Multi-corner timing analysis acceleration for iterative physical design of ICs","author":"Xing Wei W","year":"2024","unstructured":"Wei W Xing, Longze Wang, Zhelong Wang, Zhaoyu Shi, Ning Xu, Yuanqing Cheng, and Weisheng Zhao. 2024. Multi-corner timing analysis acceleration for iterative physical design of ICs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 43, 7 (2024), 2151\u20132162.","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"issue":"8","key":"e_1_3_1_15_2","first-page":"2963","article-title":"Offset-cancellation sensing-circuit-based nonvolatile flip-flop operating in near-threshold voltage region","volume":"66","author":"Song Byungkyu","year":"2019","unstructured":"Byungkyu Song, Sara Choi, Seung H Kang, and Seong-Ook Jung. 2019. Offset-cancellation sensing-circuit-based nonvolatile flip-flop operating in near-threshold voltage region. IEEE Transactions on Circuits and Systems I: Regular Papers 66, 8 (2019), 2963\u20132972.","journal-title":"IEEE Transactions on Circuits and Systems I: Regular Papers"},{"key":"e_1_3_1_16_2","article-title":"An error-resilient RISC-V microprocessor with a fully integrated DC\u2013DC voltage regulator for near-threshold operation in 28-nm CMOS","author":"Wu Bing-Chen","year":"2023","unstructured":"Bing-Chen Wu, Wei-Ting Chen, and Tsung-Te Liu. 2023. An error-resilient RISC-V microprocessor with a fully integrated DC\u2013DC voltage regulator for near-threshold operation in 28-nm CMOS. IEEE Journal of Solid-State Circuits 58, 11 (2023), 3275\u20133285.","journal-title":"IEEE Journal of Solid-State Circuits"},{"issue":"3","key":"e_1_3_1_17_2","doi-asserted-by":"crossref","first-page":"826","DOI":"10.1109\/JSSC.2019.2959494","article-title":"A bi-directional, zero-latency adaptive clocking circuit in a 28-nm wide AVFS system","volume":"55","author":"Shan Weiwei","year":"2019","unstructured":"Weiwei Shan, Wentao Dai, Liang Wan, Minyi Lu, Longxing Shi, Mingoo Seok, and Jun Yang. 2019. A bi-directional, zero-latency adaptive clocking circuit in a 28-nm wide AVFS system. IEEE Journal of Solid-State Circuits 55, 3 (2019), 826\u2013836.","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"e_1_3_1_18_2","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996664"},{"key":"e_1_3_1_19_2","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065607"},{"key":"e_1_3_1_20_2","doi-asserted-by":"publisher","DOI":"10.5555\/1899721.1899878"},{"key":"e_1_3_1_21_2","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024899"},{"key":"e_1_3_1_22_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2023.3276944"},{"issue":"4","key":"e_1_3_1_23_2","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/3572546","article-title":"IMPRoVED: Integrated method to predict postrouting setup violations in early design stages","volume":"28","author":"Kashyap Suhas Krishna","year":"2023","unstructured":"Suhas Krishna Kashyap and Sule Ozev. 2023. IMPRoVED: Integrated method to predict postrouting setup violations in early design stages. ACM Transactions on Design Automation of Electronic Systems 28, 4 (2023), 1\u201323.","journal-title":"ACM Transactions on Design Automation of Electronic Systems"},{"key":"e_1_3_1_24_2","article-title":"Multi-corner timing macro modeling with neural collaborative filtering from recommendation systems perspective","author":"Chang Kevin Kai-Chun","year":"2024","unstructured":"Kevin Kai-Chun Chang, Guan-Ting Liu, Chun-Yao Chiang, Pei-Yu Lee, and Iris Hui-Ru Jiang. 2024. Multi-corner timing macro modeling with neural collaborative filtering from recommendation systems perspective. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 43, 10 (2024), 2840\u20132853.","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"e_1_3_1_25_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2024.3379016"},{"key":"e_1_3_1_26_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.aiopen.2022.10.001"},{"key":"e_1_3_1_27_2","article-title":"Attention is all you need","volume":"30","author":"Vaswani Ashish","year":"2017","unstructured":"Ashish Vaswani, Noam Shazeer, Niki Parmar, Jakob Uszkoreit, Llion Jones, Aidan N Gomez, \u0141ukasz Kaiser, and Illia Polosukhin. 2017. Attention is all you need. Advances in Neural Information Processing Systems 30 (2017).","journal-title":"Advances in Neural Information Processing Systems"},{"key":"e_1_3_1_28_2","article-title":"Accurate interpolation of library timing parameters through recurrent convolutional neural network","author":"Hyun Daijoon","year":"2023","unstructured":"Daijoon Hyun, Younggwang Jung, and Youngsoon Shin. 2023. Accurate interpolation of library timing parameters through recurrent convolutional neural network. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 43, 1 (2023), 244\u2013248.","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"e_1_3_1_29_2","doi-asserted-by":"publisher","DOI":"10.1126\/science.1127647"},{"key":"e_1_3_1_30_2","first-page":"1","volume-title":"Proceedings of the 41st IEEE\/ACM International Conference on Computer-Aided Design","author":"Nath Siddhartha","year":"2022","unstructured":"Siddhartha Nath, Geraldo Pradipta, Corey Hu, Tian Yang, Brucek Khailany, and Haoxing Ren. 2022. Transsizer: A novel transformer-based fast gate sizer. In Proceedings of the 41st IEEE\/ACM International Conference on Computer-Aided Design. 1\u20139."},{"key":"e_1_3_1_31_2","unstructured":"S Ruder. 2017. An overview of multi-task learning in deep neural networks. arXiv:1706.05098. Retrieved from https:\/\/arxiv.org\/abs\/\/1706.05098"},{"key":"e_1_3_1_32_2","unstructured":"Zehao Huang and Naiyan Wang. 2017. Like what you like: Knowledge distill via neuron selectivity transfer. arXiv:1707.01219. Retrieved from https:\/\/arxiv.org\/abs\/\/1707.01219"},{"key":"e_1_3_1_33_2","doi-asserted-by":"publisher","DOI":"10.1145\/3649329.3656251"},{"key":"e_1_3_1_34_2","doi-asserted-by":"crossref","unstructured":"Jason Ansel Edward Yang Horace He Natalia Gimelshein Animesh Jain Michael Voznesensky Bin Bao Peter Bell David Berard Evgeni Burovski et\u00a0al. 2024. Pytorch 2: Faster machine learning through dynamic python bytecode transformation and graph compilation. In Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems 2 (2024) 929\u201347.","DOI":"10.1145\/3620665.3640366"},{"key":"e_1_3_1_35_2","volume-title":"Opencores","year":"2021","unstructured":"2021. Opencores. Retrieved from https:\/\/opencores.org\/"},{"key":"e_1_3_1_36_2","volume-title":"\u201cPrimeLib User Guide\u201d","year":"2022","unstructured":"2022. \u201cPrimeLib User Guide\u201d. Retrieved from https:\/\/www.synopsys.com\/implementation-and-signoff\/signoff\/primelib.html"},{"key":"e_1_3_1_37_2","doi-asserted-by":"publisher","DOI":"10.5555\/1953048.2078195"},{"key":"e_1_3_1_38_2","first-page":"1695","volume-title":"2013 Design, Automation & Test in Europe Conference & Exhibition (DATE)","author":"Rahimi Abbas","year":"2013","unstructured":"Abbas Rahimi, Luca Benini, and Rajesh K Gupta. 2013. Hierarchically focused guardbanding: An adaptive approach to mitigate PVT variations and aging. In 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 1695\u20131700."},{"key":"e_1_3_1_39_2","first-page":"1","volume-title":"2021 IEEE International Symposium on Circuits and Systems (ISCAS)","author":"Kalluru Hema Sai","year":"2021","unstructured":"Hema Sai Kalluru, Prasenjit Saha, Andleeb Zahra, and Zia Abbas. 2021. Algorithm driven power-timing optimization methodology for CMOS digital circuits considering PVTA variations. In 2021 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 1\u20135."}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3768166","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,3,19]],"date-time":"2026-03-19T12:17:35Z","timestamp":1773922655000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3768166"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,3,19]]},"references-count":38,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2026,7,31]]}},"alternative-id":["10.1145\/3768166"],"URL":"https:\/\/doi.org\/10.1145\/3768166","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"value":"1084-4309","type":"print"},{"value":"1557-7309","type":"electronic"}],"subject":[],"published":{"date-parts":[[2026,3,19]]},"assertion":[{"value":"2025-03-04","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2025-09-05","order":2,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2026-03-19","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}