{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,13]],"date-time":"2026-06-13T04:58:41Z","timestamp":1781326721728,"version":"3.54.1"},"reference-count":66,"publisher":"Association for Computing Machinery (ACM)","issue":"6","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Proc. ACM Manag. Data"],"published-print":{"date-parts":[[2025,12,4]]},"abstract":"<jats:p>When key-value (KV) stores use SSDs for storing a large number of items, oftentimes they also require large in-memory data structures including indices and caches to be traversed to reduce IOs. This paper considers offloading most of such data structures from the costly host DRAM to secondary memory whose latency is in the microsecond range, an order of magnitude longer than those of DIMM-mounted persistent memory and currently available CXL memory devices. While emerging microsecond-latency memory, such as one based on flash memory, is likely to cost much less than DRAM, it can significantly slow down pointer-chasing on those in-memory data structures of SSD-based KV stores if naively employed, although its impact has not been well studied. This paper analyzes and evaluates the impact of microsecond-level memory latency on the throughput of SSD-based KV operations. Our analysis finds that a well-known latency-hiding technique of software prefetching for long-latency memory from user-level threads is effective for SSD-based KV stores. The novelty of our analysis lies in modeling how the interplay between prefetching and IO affects performance, from which we derive an equation that well explains the throughput degradation due to long memory latency. The model tells us that the presence of IO in KV operations significantly enhances their tolerance to memory latency, and the throughput degradation is expected to be small even if the memory latency extends to a few microseconds, leading to a finding that SSD-based KV stores can be made latency-tolerant without devising new techniques for microsecond-latency memory. To confirm this through experiments, we design a microbenchmark as well as modify existing SSD-based KV stores so that they issue prefetches for long-latency memory from user-level threads, and run them while placing most of in-memory data structures on FPGA-based memory with adjustable microsecond latency. The results demonstrate that their KV operation throughputs for varying memory latency can be well explained by our model, and the modified KV stores achieve near-DRAM throughputs for up to a memory latency of around 5 microseconds. This suggests the possibility that SSD-based KV stores involving latency-sensitive in-memory data traversal can use microsecond-latency memory as a cost-effective alternative to the host DRAM.<\/jats:p>","DOI":"10.1145\/3769759","type":"journal-article","created":{"date-parts":[[2025,12,6]],"date-time":"2025-12-06T04:32:13Z","timestamp":1764995533000},"page":"1-28","source":"Crossref","is-referenced-by-count":0,"title":["Analysis and Evaluation of Using Microsecond-Latency Memory for In-Memory Indices and Caches in SSD-Based Key-Value Stores"],"prefix":"10.1145","volume":"3","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-9150-6503","authenticated-orcid":false,"given":"Yosuke","family":"Bando","sequence":"first","affiliation":[{"name":"Kioxia Corporation, Yokohama, Japan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0000-0704-2260","authenticated-orcid":false,"given":"Akinobu","family":"Mita","sequence":"additional","affiliation":[{"name":"Fixstars Corporation, Tokyo, Japan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0004-3610-6496","authenticated-orcid":false,"given":"Kazuhiro","family":"Hiwada","sequence":"additional","affiliation":[{"name":"Kioxia Corporation, Yokohama, Japan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0009-2988-9724","authenticated-orcid":false,"given":"Shintaro","family":"Sano","sequence":"additional","affiliation":[{"name":"Kioxia Corporation, Yokohama, Japan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0008-3031-2693","authenticated-orcid":false,"given":"Tomoya","family":"Suzuki","sequence":"additional","affiliation":[{"name":"Kioxia Corporation, Yokohama, Japan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0001-3312-3395","authenticated-orcid":false,"given":"Yu","family":"Nakanishi","sequence":"additional","affiliation":[{"name":"Kioxia Corporation, Yokohama, Japan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0004-6736-8448","authenticated-orcid":false,"given":"Kazutaka","family":"Tomida","sequence":"additional","affiliation":[{"name":"Kioxia Corporation, Yokohama, Japan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0000-4784-8234","authenticated-orcid":false,"given":"Hirotsugu","family":"Kajihara","sequence":"additional","affiliation":[{"name":"Kioxia Corporation, Yokohama, Japan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0001-0066-0469","authenticated-orcid":false,"given":"Akiyuki","family":"Kaneko","sequence":"additional","affiliation":[{"name":"Kioxia Corporation, Yokohama, Japan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0007-7193-4723","authenticated-orcid":false,"given":"Daisuke","family":"Taki","sequence":"additional","affiliation":[{"name":"Kioxia Corporation, Yokohama, Japan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0006-8703-8950","authenticated-orcid":false,"given":"Yukimasa","family":"Miyamoto","sequence":"additional","affiliation":[{"name":"Kioxia Corporation, Yokohama, Japan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0002-7278-8231","authenticated-orcid":false,"given":"Tomokazu","family":"Yoshida","sequence":"additional","affiliation":[{"name":"Fixstars Corporation, Tokyo, Japan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0001-6679-3950","authenticated-orcid":false,"given":"Tatsuo","family":"Shiozawa","sequence":"additional","affiliation":[{"name":"Kioxia Corporation, Yokohama, Japan"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2025,12,5]]},"reference":[{"key":"e_1_2_2_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/3317550.3321434"},{"key":"e_1_2_2_2_1","volume-title":"Certifying Flash Devices (SSDs). Aerospike. https:\/\/aerospike.com\/docs\/server\/operations\/plan\/ssd\/ssd_certification Retrieved","year":"2024","unstructured":"Aerospike. 2024. Certifying Flash Devices (SSDs). Aerospike. https:\/\/aerospike.com\/docs\/server\/operations\/plan\/ssd\/ssd_certification Retrieved July 10, 2024 from"},{"key":"e_1_2_2_3_1","unstructured":"Angelos Arelakis Nilesh Shah Yiannis Nikolakopoulos and Dimitrios Palyvos-Giannas. 2024. Streamlining CXL Adoption for Hyperscale Efficiency. arXiv:2404.03551 [cs.ET] https:\/\/arxiv.org\/abs\/2404.03551"},{"key":"e_1_2_2_4_1","first-page":"53","article-title":"Workload analysis of a large-scale key-value store. In the 12th ACM SIGMETRICS\/PERFORMANCE joint international conference on Measurement and Modeling of Computer Systems (SIGMETRICS)","author":"Atikoglu Berk","year":"2012","unstructured":"Berk Atikoglu, Yuehai Xu, Eitan Frachtenberg, Song Jiang, and Mike Paleczny. 2012. Workload analysis of a large-scale key-value store. In the 12th ACM SIGMETRICS\/PERFORMANCE joint international conference on Measurement and Modeling of Computer Systems (SIGMETRICS). ACM, 53-64.","journal-title":"ACM"},{"key":"e_1_2_2_5_1","volume-title":"Efficient IO with io_uring. https:\/\/kernel.dk\/io_uring.pdf Retrieved","author":"Axboe Jens","year":"2024","unstructured":"Jens Axboe. 2019. Efficient IO with io_uring. https:\/\/kernel.dk\/io_uring.pdf Retrieved July 10, 2024 from"},{"key":"e_1_2_2_6_1","volume-title":"the 1st Workshop on Interactions of NVM\/FLASH with Operating Systems and Workloads (INFLOW). ACM, 1-8.","author":"Bailey Katelin A.","unstructured":"Katelin A. Bailey, Peter Hornyack, Luis Ceze, Steven D. Gribble, and Henry M. Levy. 2013. Exploring storage class memory with key value stores. In the 1st Workshop on Interactions of NVM\/FLASH with Operating Systems and Workloads (INFLOW). ACM, 1-8."},{"key":"e_1_2_2_7_1","doi-asserted-by":"publisher","DOI":"10.14778\/3461535.3461543"},{"key":"e_1_2_2_8_1","volume-title":"Ganger","author":"Berg Benjamin","year":"2020","unstructured":"Benjamin Berg, Daniel S. Berger, Sara McAllister, Isaac Grosof, Sathya Gunasekar, Jimmy Lu, Michael Uhlar, Jim Carrig, Nathan Beckmann, Mor Harchol-Balter, and Gregory R. Ganger. 2020. The CacheLib Caching Engine: Design and Experiences at Scale. In the 14th USENIX Symposium on Operating Systems Design and Implementation (OSDI). USENIX Association, 769-786."},{"key":"e_1_2_2_9_1","first-page":"209","volume-title":"18th USENIX Conference on File and Storage Technologies (FAST 20)","author":"Cao Zhichao","unstructured":"Zhichao Cao, Siying Dong, Sagar Vemuri, and David H.C. Du. 2020. Characterizing, Modeling, and Benchmarking RocksDB Key-Value Workloads at Facebook. In 18th USENIX Conference on File and Storage Technologies (FAST 20). USENIX Association, Santa Clara, CA, 209-223. https:\/\/www.usenix.org\/conference\/fast20\/presentation\/cao-zhichao"},{"key":"e_1_2_2_10_1","unstructured":"Bob Chen. 2023. 200 Lines of Code to Rewrite the 600'000 Lines RocksDB into a Coroutine Program. Alibaba Cloud. https:\/\/www.alibabacloud.com\/blog\/200-lines-of-code-to-rewrite-the-600000-lines-rocksdb-into-a-coroutine-program_599622 Retrieved November 11 2024 from"},{"key":"e_1_2_2_11_1","volume-title":"Taming the Killer Microsecond. In The 51st Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO). IEEE","author":"Cho Shenghsun","year":"2018","unstructured":"Shenghsun Cho, Amoghavarsha Suresh, Tapti Palit, Michael Ferdman, and Nima Honarmand. 2018. Taming the Killer Microsecond. In The 51st Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO). IEEE, Fukuoka, Japan."},{"key":"e_1_2_2_12_1","volume-title":"Compute Express Link","author":"The CXL Consortium","year":"2024","unstructured":"The CXL Consortium. 2024. Compute Express Link. The CXL Consortium. https:\/\/www.computeexpresslink.org\/ Retrieved July 10, 2024 from"},{"key":"e_1_2_2_13_1","volume-title":"Intel 64 and IA-32 Architectures Software Developer's Manual","author":"Intel Corporation","unstructured":"Intel Corporation. 2025. Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide, Part 2., Intel Corporation. https:\/\/www.intel.com\/content\/www\/us\/en\/developer\/articles\/technical\/intel-sdm.html Retrieved July 24, 2025 from"},{"key":"e_1_2_2_14_1","volume-title":"Memcheck: a memory error detector. Valgrind Developers. https:\/\/valgrind.org\/docs\/manual\/mc-manual.html Retrieved","author":"Developers Valgrind","year":"2024","unstructured":"Valgrind Developers. 2024. 4. Memcheck: a memory error detector. Valgrind Developers. https:\/\/valgrind.org\/docs\/manual\/mc-manual.html Retrieved July 10, 2024 from"},{"key":"e_1_2_2_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2022.3188268"},{"key":"e_1_2_2_16_1","first-page":"v1","article-title":"Key-Value Stores on Flash Storage Devices: A Survey","volume":"2205","author":"Doekemeijer Krijn","year":"2022","unstructured":"Krijn Doekemeijer and Animesh Trivedi. 2022. Key-Value Stores on Flash Storage Devices: A Survey. Technical Report 2205.07975v1. Vrije Universiteit Amsterdam.","journal-title":"Technical Report"},{"key":"e_1_2_2_17_1","first-page":"33","article-title":"Evolution of Development Priorities in Key-value Stores Serving Large-scale Applications: The RocksDB Experience. In the 19th USENIX Conference on File and Storage Technologies (FAST)","author":"Dong Siying","year":"2021","unstructured":"Siying Dong, Andrew Kryczka, Yanqin Jin, and Michael Stumm. 2021. Evolution of Development Priorities in Key-value Stores Serving Large-scale Applications: The RocksDB Experience. In the 19th USENIX Conference on File and Storage Technologies (FAST). USENIX Association, 33-49.","journal-title":"USENIX Association"},{"key":"e_1_2_2_18_1","doi-asserted-by":"publisher","DOI":"10.14778\/3583140.3583167"},{"key":"e_1_2_2_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/3582016.3582031"},{"key":"e_1_2_2_20_1","first-page":"1037","volume-title":"2022 USENIX Annual Technical Conference (USENIX ATC 22)","author":"Elhemali Mostafa","year":"2022","unstructured":"Mostafa Elhemali, Niall Gallagher, Nick Gordon, Joseph Idziorek, Richard Krog, Colin Lazier, Erben Mo, Akhilesh Mritunjai, Somasundaram Perianayagam, Tim Rath, Swami Sivasubramanian, James Christopher Sorenson III, Sroaj Sosothikul, Doug Terry, and Akshat Vig. 2022. Amazon DynamoDB: A Scalable, Predictably Performant, and Fully Managed NoSQL Database Service. In 2022 USENIX Annual Technical Conference (USENIX ATC 22). USENIX Association, Carlsbad, CA, 1037-1048. https:\/\/www.usenix.org\/conference\/atc22\/presentation\/elhemali"},{"key":"e_1_2_2_21_1","doi-asserted-by":"publisher","DOI":"10.1287\/mnsc.21.11.1338"},{"key":"e_1_2_2_22_1","doi-asserted-by":"publisher","DOI":"10.14778\/3430915.3430932"},{"key":"e_1_2_2_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2016.7753257"},{"key":"e_1_2_2_24_1","doi-asserted-by":"publisher","DOI":"10.14778\/3632093.3632117"},{"key":"e_1_2_2_25_1","volume-title":"2018 USENIX Annual Technical Conference (ATC). USENIX Association, 967-979","author":"Huang Yihe","year":"2018","unstructured":"Yihe Huang, Matej Pavlovic, Virendra Marathe, Margo Seltzer, Tim Harris, and Steve Byan. 2018. Closing the performance gap between volatile and persistent key-value stores using cross-referencing logs. In 2018 USENIX Annual Technical Conference (ATC). USENIX Association, 967-979."},{"key":"e_1_2_2_26_1","volume-title":"Zixuan Wang, Yi Xu, Subramanya R. Dulloor, Jishen Zhao, and Steven Swanson.","author":"Izraelevitz Joseph","year":"2019","unstructured":"Joseph Izraelevitz, Jian Yang, Lu Zhang, Juno Kim, Xiao Liu, Amirsaman Memaripour, Yun Joon Soh, Zixuan Wang, Yi Xu, Subramanya R. Dulloor, Jishen Zhao, and Steven Swanson. 2019. Basic Performance Measurements of the Intel Optane DC Persistent Memory Module. arXiv:1903.05714 [cs.DC] https:\/\/arxiv.org\/abs\/1903.05714"},{"key":"e_1_2_2_27_1","volume-title":"SLM-DB: Single-Level Key-Value Store with Persistent Memory. In the 17th USENIX Conference on File and Storage Technologies (FAST). USENIX Association, 191-204","author":"Kaiyrakhmet Olzhas","year":"2019","unstructured":"Olzhas Kaiyrakhmet, Songyi Lee, Beomseok Nam, Sam H. Noh, and Young-Ri Choi. 2019. SLM-DB: Single-Level Key-Value Store with Persistent Memory. In the 17th USENIX Conference on File and Storage Technologies (FAST). USENIX Association, 191-204."},{"key":"e_1_2_2_28_1","volume-title":"Proceedings of the 2018 USENIX Conference on Usenix Annual Technical Conference (Boston, MA, USA) (USENIX ATC '18). USENIX Association, USA, 993-1005","author":"Kannan Sudarsun","year":"2018","unstructured":"Sudarsun Kannan, Nitish Bhat, Ada Gavrilovska, Andrea Arpaci-Dusseau, and Remzi Arpaci-Dusseau. 2018. Redesigning LSMs for nonvolatile memory with NoveLSM. In Proceedings of the 2018 USENIX Conference on Usenix Annual Technical Conference (Boston, MA, USA) (USENIX ATC '18). USENIX Association, USA, 993-1005."},{"key":"e_1_2_2_29_1","volume-title":"2021 USENIX Annual Technical Conference. USENIX Association.","author":"Kassa Hiwot Tadese","year":"2021","unstructured":"Hiwot Tadese Kassa, Jason Akers, Mrinmoy Ghosh, Zhichao Cao, Vaibhav Gogte, and Ronald Dreslinski. 2021. Improving Performance of Flash Based Key-Value Stores Using Storage Class Memory as a Volatile Memory Extension. In 2021 USENIX Annual Technical Conference. USENIX Association."},{"key":"e_1_2_2_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2023.3240774"},{"key":"e_1_2_2_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/3662010.3663451"},{"key":"e_1_2_2_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/3592980.3595311"},{"key":"e_1_2_2_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/3575693.3578835"},{"key":"e_1_2_2_34_1","volume-title":"Stackful Coroutine Made Fast. Alibaba Cloud. https:\/\/photonlibos.github.io\/blog-20241014\/Stackful_Coroutine_Made_Fast.pdf Retrieved","author":"Li Huiba","year":"2024","unstructured":"Huiba Li, Rui Du, Sinan Lin, and Windsor Hsu. 2024. Stackful Coroutine Made Fast. Alibaba Cloud. https:\/\/photonlibos.github.io\/blog-20241014\/Stackful_Coroutine_Made_Fast.pdf Retrieved November 11, 2024 from"},{"key":"e_1_2_2_35_1","doi-asserted-by":"publisher","DOI":"10.1287\/opre.1110.0940"},{"key":"e_1_2_2_36_1","unstructured":"Jinshu Liu Hamid Hadian Hanchen Xu Daniel S. Berger and Huaicheng Li. 2024. Dissecting CXL Memory Performance at Scale: Analysis Modeling and Optimization. arXiv:2409.14317 [cs.OS] https:\/\/arxiv.org\/abs\/2409.14317"},{"key":"e_1_2_2_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/3736227.3736231"},{"key":"e_1_2_2_38_1","volume-title":"Proceedings of the 6th USENIX Conference on Hot Topics in Storage and File Systems","author":"M\u00e1rmol Leonardo","year":"2014","unstructured":"Leonardo M\u00e1rmol, Swaminathan Sundararaman, Nisha Talagala, Raju Rangaswami, Sushma Devendrappa, Bharath Ramsundar, and Sriram Ganesan. 2014. NVMKV: a scalable and lightweight flash aware key-value store. In Proceedings of the 6th USENIX Conference on Hot Topics in Storage and File Systems (Philadelphia, PA) (HotStorage'14). USENIX Association, USA, 8."},{"key":"e_1_2_2_39_1","volume-title":"Proceedings of the thirteenth ACM symposium on Operating systems principles (SOSP). ACM, 110-121","author":"Marsh Brian D.","unstructured":"Brian D. Marsh, Michael L. Scott, Thomas J. LeBlanc, and Evangelos P. Markatos. 1991. First-class user-level threads. In Proceedings of the thirteenth ACM symposium on Operating systems principles (SOSP). ACM, 110-121."},{"key":"e_1_2_2_40_1","volume-title":"TPP: Transparent Page Placement for CXL-Enabled Tiered-Memory. In the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). ACM, 742-755","author":"Maruf Hasan Al","year":"2023","unstructured":"Hasan Al Maruf, Hao Wang, Abhishek Dhanotia, Johannes Weiner, Niket Agarwal, Pallab Bhattacharya, Chris Petersen, Mosharaf Chowdhury, Shobhit Kanaujia, and Prakash Chauhan. 2023. TPP: Transparent Page Placement for CXL-Enabled Tiered-Memory. In the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). ACM, 742-755."},{"key":"e_1_2_2_41_1","volume-title":"Kangaroo: Caching Billions of Tiny Objects on Flash. In the ACM SIGOPS 28th Symposium on Operating Systems Principles (SOSP). ACM, 243-262","author":"McAllister Sara","unstructured":"Sara McAllister, Benjamin Berg, Julian Tutuncu-Macias, Juncheng Yang, Sathya Gunasekar, Jimmy Lu, Daniel S. Berger, Nathan Beckmann, and Gregory R. Ganger. 2021. Kangaroo: Caching Billions of Tiny Objects on Flash. In the ACM SIGOPS 28th Symposium on Operating Systems Principles (SOSP). ACM, 243-262."},{"key":"e_1_2_2_42_1","volume-title":"Price and Performance Changes of Computer Technology with Time. https:\/\/jcmit.net\/index.htm Retrieved","author":"McCallum John C.","year":"2024","unstructured":"John C. McCallum. 2024. Price and Performance Changes of Computer Technology with Time. https:\/\/jcmit.net\/index.htm Retrieved November 11, 2024 from"},{"key":"e_1_2_2_43_1","doi-asserted-by":"publisher","DOI":"10.1109\/TKDE.2020.3027191"},{"key":"e_1_2_2_44_1","doi-asserted-by":"publisher","DOI":"10.1145\/3617581"},{"key":"e_1_2_2_45_1","doi-asserted-by":"publisher","DOI":"10.1016\/0743-7315(91)90014-Z"},{"key":"e_1_2_2_46_1","doi-asserted-by":"publisher","DOI":"10.1145\/3620678.3624667"},{"key":"e_1_2_2_47_1","doi-asserted-by":"publisher","DOI":"10.1145\/2882903.2915251"},{"key":"e_1_2_2_48_1","doi-asserted-by":"publisher","DOI":"10.1145\/3627703.3650075"},{"key":"e_1_2_2_49_1","volume-title":"Samsung Electronics Co","year":"2018","unstructured":"Ltd. Samsung Electronics Co., 2018. Samsung Z-SSD SZ985. Samsung Electronics Co., Ltd. https:\/\/download.semiconductor.samsung.com\/resources\/brochure\/Brochure_Samsung_S-ZZD_SZ985_1804.pdf Retrieved February 4, 2025 from"},{"key":"e_1_2_2_50_1","first-page":"962","article-title":"GPU Graph Processing on CXL-Based Microsecond-Latency External Memory. In The SC '23 Workshops of The International Conference on High Performance Computing","author":"Sano Shintaro","year":"2023","unstructured":"Shintaro Sano, Yosuke Bando, Kazuhiro Hiwada, Hirotsugu Kajihara, Tomoya Suzuki, Yu Nakanishi, Daisuke Taki, Akiyuki Kaneko, and Tatsuo Shiozawa. 2023. GPU Graph Processing on CXL-Based Microsecond-Latency External Memory. In The SC '23 Workshops of The International Conference on High Performance Computing, Network, Storage, and Analysis. ACM, 962-972.","journal-title":"Network, Storage, and Analysis. ACM"},{"key":"e_1_2_2_51_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2017.2766062"},{"key":"e_1_2_2_52_1","volume-title":"CMM-H: CXL-Enabled Large Scale Memory Expansion with a Hybrid NAND\/DRAM Solution","author":"Soltaniyeh Reza","unstructured":"Reza Soltaniyeh, Gongjin Sun, Caroline Kahn, Hingkwan Huen, Senthil Murugesapandian, Amir Beygi, Andrew Chang, Xuebin Yao, and Ramdas Kachare. 2025. CMM-H: CXL-Enabled Large Scale Memory Expansion with a Hybrid NAND\/DRAM Solution. Samsung Electronics Co., Ltd. https:\/\/download.semiconductor.samsung.com\/resources\/white-paper\/CMM-H_Whitepaper_10149503034923.pdf Retrieved July 15, 2025 from"},{"key":"e_1_2_2_53_1","doi-asserted-by":"publisher","DOI":"10.14778\/3007263.3007276"},{"key":"e_1_2_2_54_1","volume-title":"Demystifying CXL Memory with Genuine CXL-Ready Systems and Devices. In The 56th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO). ACM, 105-121","author":"Sun Yan","year":"2023","unstructured":"Yan Sun, Yifan Yuan, Zeduo Yu, Reese Kuper, Chihun Song, Jinghan Huang, Houxiang Ji, Siddharth Agarwal, Jiaqi Lou, Ipoom Jeong, Ren Wang, Jung Ho Ahn, Tianyin Xu, and Nam Sung Kim. 2023. Demystifying CXL Memory with Genuine CXL-Ready Systems and Devices. In The 56th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO). ACM, 105-121."},{"key":"e_1_2_2_55_1","doi-asserted-by":"publisher","DOI":"10.14778\/3457390.3457397"},{"key":"e_1_2_2_56_1","volume-title":"ELI5: Folly - Battle-Tested C Library. Meta Platforms","author":"Vinnik Dmitry","year":"2021","unstructured":"Dmitry Vinnik. 2021. ELI5: Folly - Battle-Tested C Library. Meta Platforms, Inc. https:\/\/developers.facebook.com\/blog\/post\/2021\/05\/24\/eli5-folly-battle-tested-c-plus-plus-library\/ Retrieved July 10, 2024 from"},{"key":"e_1_2_2_57_1","volume-title":"Evaluating Emerging CXL-enabled Memory Pooling for HPC Systems. In IEEE\/ACM Workshop on Memory Centric High Performance Computing (MCHPC). 11-20","author":"Wahlgren Jacob","unstructured":"Jacob Wahlgren, Maya Gokhale, and Ivy B. Peng. 2022. Evaluating Emerging CXL-enabled Memory Pooling for HPC Systems. In IEEE\/ACM Workshop on Memory Centric High Performance Computing (MCHPC). 11-20."},{"key":"e_1_2_2_58_1","volume-title":"Sungjoo Park, and Jishen Zhao.","author":"Wang Zixuan","year":"2024","unstructured":"Zixuan Wang, Suyash Mahar, Luyi Li, Jangseon Park, Jinpyo Kim, Theodore Michailidis, Yue Pan, Tajana Rosing, Dean Tullsen, Steven Swanson, Kyung Chang Ryoo, Sungjoo Park, and Jishen Zhao. 2024. The Hitchhiker's Guide to Programming and Optimizing CXL-Based Heterogeneous Systems. arXiv:2411.02814 [cs.PF] https:\/\/arxiv.org\/abs\/2411.02814"},{"key":"e_1_2_2_59_1","doi-asserted-by":"publisher","DOI":"10.1145\/3240302.3240303"},{"key":"e_1_2_2_60_1","volume-title":"LLC. https:\/\/files.futurememorystorage.com\/proceedings\/2018\/20180806_PreConC_Webb.pdf Retrieved","author":"Webb Mark","year":"2024","unstructured":"Mark Webb. 2018. Overview of Persistent Memory. MKW Ventures Consulting, LLC. https:\/\/files.futurememorystorage.com\/proceedings\/2018\/20180806_PreConC_Webb.pdf Retrieved November 11, 2024 from"},{"key":"e_1_2_2_61_1","volume-title":"2017 USENIX Annual Technical Conference (ATC). USENIX Association, 349-362","author":"Xia Fei","year":"2017","unstructured":"Fei Xia, Dejun Jiang, Jin Xiong, and Ninghui Sun. 2017. HiKV: A hybrid index key-value store for DRAM-NVM memory systems. In 2017 USENIX Annual Technical Conference (ATC). USENIX Association, 349-362."},{"key":"e_1_2_2_62_1","volume-title":"the 2020 USENIX Conference on Usenix Annual Technical Conference (ATC). USENIX Association, 17-31","author":"Yao Ting","year":"2020","unstructured":"Ting Yao, Yiwen Zhang, Jiguang Wan, Qiu Cui, Liu Tang, Hong Jiang, Changsheng Xie, and Xubin He. 2020. MatrixKV: reducing write stalls and write amplification in LSM-tree based KV stores with a matrix container in NVM. In the 2020 USENIX Conference on Usenix Annual Technical Conference (ATC). USENIX Association, 17-31."},{"key":"e_1_2_2_63_1","volume-title":"User Interface for Resource Control feature","author":"Yu Fenghua","unstructured":"Fenghua Yu, Tony Luck, and Vikas Shivappa. 2016. User Interface for Resource Control feature. Intel Corporation. https:\/\/www.kernel.org\/doc\/html\/v5.11\/x86\/resctrl.html Retrieved July 24, 2025 from"},{"key":"e_1_2_2_64_1","doi-asserted-by":"publisher","DOI":"10.1145\/3447786.3456237"},{"key":"e_1_2_2_65_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICDE60146.2024.00046"},{"key":"e_1_2_2_66_1","doi-asserted-by":"publisher","DOI":"10.1145\/3673038.3673153"}],"container-title":["Proceedings of the ACM on Management of Data"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3769759","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,6,13]],"date-time":"2026-06-13T04:49:25Z","timestamp":1781326165000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3769759"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,12,4]]},"references-count":66,"journal-issue":{"issue":"6","published-print":{"date-parts":[[2025,12,4]]}},"alternative-id":["10.1145\/3769759"],"URL":"https:\/\/doi.org\/10.1145\/3769759","relation":{},"ISSN":["2836-6573"],"issn-type":[{"value":"2836-6573","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,12,4]]}}}