{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,20]],"date-time":"2026-06-20T21:46:29Z","timestamp":1781991989821,"version":"3.54.5"},"reference-count":53,"publisher":"Association for Computing Machinery (ACM)","issue":"1","funder":[{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation","doi-asserted-by":"crossref","award":["3065.001, 3106.001, and 3198.001"],"award-info":[{"award-number":["3065.001, 3106.001, and 3198.001"]}],"id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2026,1,31]]},"abstract":"<jats:p>Systolic arrays are a popular choice for accelerating deep neural networks (DNNs) due to their inherent parallelism and efficient data reuse. However, ensuring the reliability of these DNN accelerators is crucial, as hardware faults can significantly degrade inferencing accuracy. Because systolic arrays utilize a large number of processing elements (PEs) for parallel processing, dataflow involving faulty PEs is especially of concern. Error propagation through PEs can reduce inferencing accuracy for DNN workloads. Although fault detection and repair techniques have been proposed to enhance the robustness of systolic arrays, fault localization remains an open problem. We propose a fault tolerance framework including run-time based fault detection and fault localization, both leveraging functional data to generate checksums on-the-fly. This approach enables error detection and localization during normal operation, avoiding the need for dedicated test patterns or additional downtime. Experimental evaluation shows that the proposed fault localization architecture incurs an area overhead less than 2% for a 256\u00d7 256 systolic array. In simulations, the proposed method achieves 100% fault detection and localization in a 256\u00d7 256 systolic array.<\/jats:p>","DOI":"10.1145\/3770920","type":"journal-article","created":{"date-parts":[[2025,10,8]],"date-time":"2025-10-08T11:28:44Z","timestamp":1759922924000},"page":"1-27","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Runtime Fault Localization in Deep Neural Network Accelerators"],"prefix":"10.1145","volume":"31","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-4075-3499","authenticated-orcid":false,"given":"Wei-Kai","family":"Liu","sequence":"first","affiliation":[{"name":"Electrical and Computer Engineering, Duke University","place":["Durham, United States"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7079-5281","authenticated-orcid":false,"given":"Jonti","family":"Talukdar","sequence":"additional","affiliation":[{"name":"Electrical and Computer Engineering, Duke University","place":["Durham, United States"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7642-3638","authenticated-orcid":false,"given":"Benjamin","family":"Tan","sequence":"additional","affiliation":[{"name":"Electrical and Software Engineering, University of Calgary","place":["Calgary, Canada"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4475-6435","authenticated-orcid":false,"given":"Krishnendu","family":"Chakrabarty","sequence":"additional","affiliation":[{"name":"Arizona State University","place":["Tempe, United States"]}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2025,11,11]]},"reference":[{"key":"e_1_3_1_2_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783725"},{"key":"e_1_3_1_3_2","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898082"},{"key":"e_1_3_1_4_2","doi-asserted-by":"publisher","DOI":"10.23919\/DATE56975.2023.10136985"},{"key":"e_1_3_1_5_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.jpdc.2008.12.002"},{"key":"e_1_3_1_6_2","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2022.3159089"},{"key":"e_1_3_1_7_2","doi-asserted-by":"publisher","DOI":"10.5555\/1950815.1950906"},{"key":"e_1_3_1_8_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2022.3166108"},{"key":"e_1_3_1_9_2","doi-asserted-by":"publisher","DOI":"10.1145\/2654822.2541967"},{"key":"e_1_3_1_10_2","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001177"},{"key":"e_1_3_1_11_2","doi-asserted-by":"crossref","unstructured":"Natalia Cherezova Artur Jutman and Maksim Jenihhin. 2025. FORTALESA: Fault-Tolerant reconfigurable systolic array for DNN inference. arXiv:2503.04426. Retrieved from https:\/\/arxiv.org\/abs\/2503.04426","DOI":"10.1016\/j.micpro.2025.105222"},{"key":"e_1_3_1_12_2","article-title":"Efficient systolic-array redundancy architecture for offline\/online repair","author":"Cho Keewon","year":"2020","unstructured":"Keewon Cho, Ingeol Lee, Hyeonchan Lim, and Sungho Kang. 2020. Efficient systolic-array redundancy architecture for offline\/online repair. Electronics (2020).","journal-title":"Electronics"},{"key":"e_1_3_1_13_2","unstructured":"Harish Dattatraya Dixit Sneha Pendharkar Matt Beadon Chris Mason Tejasvi Chakravarthy Bharath Muthiah and Sriram Sankar. 2021. Silent data corruptions at scale. arXiv:2102.11245. Retrieved from https:\/\/arxiv.org\/abs\/2102.11245"},{"key":"e_1_3_1_14_2","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS50870.2020.9159734"},{"key":"e_1_3_1_15_2","article-title":"Making convolutions resilient via algorithm-based error detection techniques","author":"Hari Siva Kumar Sastry","year":"2021","unstructured":"Siva Kumar Sastry Hari, Michael B. Sullivan, Timothy Tsai, and Stephen W. Keckler. 2021. Making convolutions resilient via algorithm-based error detection techniques. IEEE Transactions on Dependable and Secure Computing (2021).","journal-title":"IEEE Transactions on Dependable and Secure Computing"},{"key":"e_1_3_1_16_2","doi-asserted-by":"publisher","DOI":"10.1109\/ETS56758.2023.10173972"},{"key":"e_1_3_1_17_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCRD54409.2022.9730377"},{"key":"e_1_3_1_18_2","article-title":"Algorithm-based fault tolerance for matrix operations","author":"Huang Kuang-Hua","year":"1984","unstructured":"Kuang-Hua Huang and Jacob A. Abraham. 1984. Algorithm-based fault tolerance for matrix operations. IEEE Transactions on Computers (1984).","journal-title":"IEEE Transactions on Computers"},{"key":"e_1_3_1_19_2","article-title":"Generating systolic array accelerators with reusable blocks","author":"Jia Liancheng","year":"2020","unstructured":"Liancheng Jia, Liqiang Lu, Xuechao Wei, and Yun Liang. 2020. Generating systolic array accelerators with reusable blocks. IEEE Micro (2020).","journal-title":"IEEE Micro"},{"key":"e_1_3_1_20_2","doi-asserted-by":"crossref","DOI":"10.1109\/2.241423","article-title":"General-purpose systolic arrays","author":"Johnson K. T.","year":"1993","unstructured":"K. T. Johnson, A. R. Hurson, and B. Shirazi. 1993. General-purpose systolic arrays. Computer (1993).","journal-title":"Computer"},{"key":"e_1_3_1_21_2","volume-title":"Proceedings of the International Symposium on Computer Architecture","author":"Jouppi Norman P.","year":"2017","unstructured":"Norman P. Jouppi, Cliff Young, Nishant Patil, David Patterson, Gaurav Agrawal, Raminder Bajwa, Sarah Bates, Suresh Bhatia, Nan Boden, Al Borchers, et\u00a0al. 2017. In-datacenter performance analysis of a tensor processing unit. In Proceedings of the International Symposium on Computer Architecture."},{"key":"e_1_3_1_22_2","article-title":"Toward functional safety of systolic array-based deep learning hardware accelerators","author":"Kundu Shamik","year":"2021","unstructured":"Shamik Kundu, Suvadeep Banerjee, Arnab Raha, Suriyaprakash Natarajan, and Kanad Basu. 2021. Toward functional safety of systolic array-based deep learning hardware accelerators. IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2021).","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"key":"e_1_3_1_23_2","article-title":"Diagnnose: Toward error localization in deep learning hardware-based on vta-tvm stack","author":"Kundu Shamik","year":"2023","unstructured":"Shamik Kundu, Suvadeep Banerjee, Arnab Raha, Suriyaprakash Natarajan, and Kanad Basu. 2023. Diagnnose: Toward error localization in deep learning hardware-based on vta-tvm stack. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2023).","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"e_1_3_1_24_2","article-title":"Trouble-shooting at gan point: Improving functional safety in deep learning accelerators","author":"Kundu Shamik","year":"2023","unstructured":"Shamik Kundu, Suvadeep Banerjee, Arnab Raha, Fei Su, Suriyaprakash Natarajan, and Kanad Basu. 2023. Trouble-shooting at gan point: Improving functional safety in deep learning accelerators. IEEE Transactions on Computers (2023).","journal-title":"IEEE Transactions on Computers"},{"key":"e_1_3_1_25_2","volume-title":"Proceedings of the ACM\/IEEE Design Automation Conference","author":"Kundu Shamik","year":"2024","unstructured":"Shamik Kundu, Mirazul Haque, Sanjay Das, Wei Yang, and Kanad Basu. 2024. MENDNet: Just-in-time fault detection and mitigation in AI systems with uncertainty quantification and multi-exit networks. In Proceedings of the ACM\/IEEE Design Automation Conference."},{"key":"e_1_3_1_26_2","article-title":"STRAIT: Self-test and self-recovery for AI accelerator","author":"Lee Hayoung","year":"2023","unstructured":"Hayoung Lee, Jihye Kim, Jongho Park, and Sungho Kang. 2023. STRAIT: Self-test and self-recovery for AI accelerator. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2023).","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"e_1_3_1_27_2","doi-asserted-by":"publisher","DOI":"10.1145\/3126908.3126964"},{"key":"e_1_3_1_28_2","article-title":"Efficient error detection for matrix multiplication with systolic arrays on FPGAs","author":"Libano Fabiano","year":"2023","unstructured":"Fabiano Libano, Paolo Rech, and John Brunhaver. 2023. Efficient error detection for matrix multiplication with systolic arrays on FPGAs. IEEE Transactions on Computers (2023).","journal-title":"IEEE Transactions on Computers"},{"key":"e_1_3_1_29_2","article-title":"HyCA: A hybrid computing architecture for fault-tolerant deep learning","author":"Liu Cheng","year":"2021","unstructured":"Cheng Liu, Cheng Chu, Dawen Xu, Ying Wang, Qianlong Wang, Huawei Li, Xiaowei Li, and Kwang-Ting Cheng. 2021. HyCA: A hybrid computing architecture for fault-tolerant deep learning. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2021).","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"e_1_3_1_30_2","volume-title":"Proceedings of the 2024 IEEE 33rd Asian Test Symposium","author":"Liu Wei-Kai","year":"2024","unstructured":"Wei-Kai Liu, Jonti Talukdar, Benjamin Tan, and Krishnendu Chakrabarty. 2024. Effective runtime fault detection for DNN accelerators. In Proceedings of the 2024 IEEE 33rd Asian Test Symposium."},{"key":"e_1_3_1_31_2","article-title":"Hardware-supported patching of security bugs in hardware IP blocks","author":"Liu Wei-Kai","year":"2022","unstructured":"Wei-Kai Liu, Benjamin Tan, Jason M. Fung, Ramesh Karri, and Krishnendu Chakrabarty. 2022. Hardware-supported patching of security bugs in hardware IP blocks. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2022).","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"e_1_3_1_32_2","article-title":"Highly fault-tolerant systolic-array-based matrix multiplication","author":"Lu Hsin-Chen","year":"2024","unstructured":"Hsin-Chen Lu, Liang-Ying Su, and Shih-Hsu Huang. 2024. Highly fault-tolerant systolic-array-based matrix multiplication. Electronics (2024).","journal-title":"Electronics"},{"key":"e_1_3_1_33_2","doi-asserted-by":"crossref","DOI":"10.1016\/j.micpro.2022.104441","article-title":"Review of ASIC accelerators for deep neural network","author":"Machupalli Raju","year":"2022","unstructured":"Raju Machupalli, Masum Hossain, and Mrinal Mandal. 2022. Review of ASIC accelerators for deep neural network. Microprocessors and Microsystems (2022).","journal-title":"Microprocessors and Microsystems"},{"key":"e_1_3_1_34_2","volume-title":"Proceedings of the International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems","author":"Mummidi Chandra Sekhar","year":"2024","unstructured":"Chandra Sekhar Mummidi, Sandeep Bal, and Sandip Kundu. 2024. A novel self-repair mechanism for tiled matrix multiplication unit. In Proceedings of the International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems."},{"key":"e_1_3_1_35_2","article-title":"SSDMNV2: A real time DNN-based face mask detection system using single shot multibox detector and MobileNetV2","author":"Nagrath Preeti","year":"2021","unstructured":"Preeti Nagrath, Rachna Jain, Agam Madan, Rohan Arora, Piyush Kataria, and Jude Hemanth. 2021. SSDMNV2: A real time DNN-based face mask detection system using single shot multibox detector and MobileNetV2. Sustainable Cities and Society (2021).","journal-title":"Sustainable Cities and Society"},{"key":"e_1_3_1_36_2","volume-title":"Proceedings of the IEEE Asian Test Symposium","author":"Ozen Elbruz","year":"2019","unstructured":"Elbruz Ozen and Alex Orailoglu. 2019. Sanity-check: Boosting the reliability of safety-critical deep neural network applications. In Proceedings of the IEEE Asian Test Symposium."},{"key":"e_1_3_1_37_2","volume-title":"Proceedings of the International Conference on Computer-Aided Design","author":"Ozen Elbruz","year":"2020","unstructured":"Elbruz Ozen and Alex Orailoglu. 2020. Just say zero: Containing critical bit-error propagation in deep neural networks with anomalous feature suppression. In Proceedings of the International Conference on Computer-Aided Design."},{"key":"e_1_3_1_38_2","article-title":"Architecting decentralization and customizability in DNN accelerators for hardware defect adaptation","author":"Ozen Elbruz","year":"2022","unstructured":"Elbruz Ozen and Alex Orailoglu. 2022. Architecting decentralization and customizability in DNN accelerators for hardware defect adaptation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2022).","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"e_1_3_1_39_2","volume-title":"Proceedings of the IEEE Symposium on Security and Privacy","author":"Pearce Hammond","year":"2022","unstructured":"Hammond Pearce, Baleegh Ahmad, Benjamin Tan, Brendan Dolan-Gavitt, and Ramesh Karri. 2022. Asleep at the keyboard? assessing the security of GitHub Copilot\u2019s code contributions. In Proceedings of the IEEE Symposium on Security and Privacy."},{"key":"e_1_3_1_40_2","doi-asserted-by":"crossref","unstructured":"Ahmad E. L. Sallab Mohammed Abdou Etienne Perot and Senthil Yogamani. 2017. Deep reinforcement learning framework for autonomous driving. arXiv:1704.02532. Retrieved from https:\/\/arxiv.org\/abs\/1704.02532","DOI":"10.2352\/ISSN.2470-1173.2017.19.AVM-023"},{"key":"e_1_3_1_41_2","unstructured":"Ananda Samajdar Yuhao Zhu Paul Whatmough Matthew Mattina and Tushar Krishna. 2019. SCALE-Sim: Systolic CNN accelerator simulator. arXiv:1811.02883. Retrieved from https:\/\/arxiv.org\/abs\/1811.02883"},{"key":"e_1_3_1_42_2","volume-title":"Proceedings of the International Conference on Computer, Communications and Electronics","author":"Singh Shashi Pal","year":"2017","unstructured":"Shashi Pal Singh, Ajai Kumar, Hemant Darbari, Lenali Singh, Anshika Rastogi, and Shikha Jain. 2017. Machine translation using deep learning: An overview. In Proceedings of the International Conference on Computer, Communications and Electronics."},{"key":"e_1_3_1_43_2","doi-asserted-by":"crossref","DOI":"10.1109\/ACCESS.2021.3094741","article-title":"Test architecture for systolic array of edge-based AI accelerator","author":"Solangi Umair Saeed","year":"2021","unstructured":"Umair Saeed Solangi, Muhammad Ibtesam, Muhammad Adil Ansari, Jinuk Kim, and Sungju Park. 2021. Test architecture for systolic array of edge-based AI accelerator. IEEE Access (2021).","journal-title":"IEEE Access"},{"key":"e_1_3_1_44_2","article-title":"Testability and dependability of AI hardware: Survey, trends, challenges, and perspectives","author":"Su Fei","year":"2023","unstructured":"Fei Su, Chunsheng Liu, and Haralampos-G. Stratigopoulos. 2023. Testability and dependability of AI hardware: Survey, trends, challenges, and perspectives. IEEE Design and Test (2023).","journal-title":"IEEE Design and Test"},{"key":"e_1_3_1_45_2","volume-title":"Proceedings of the IEEE Pacific Rim International Symposium on Dependable Computing","author":"Takanami Itsuo","year":"2017","unstructured":"Itsuo Takanami and Masaru Fukushi. 2017. A built-in circuit for self-repairing mesh-connected processor arrays with spares on diagonal. In Proceedings of the IEEE Pacific Rim International Symposium on Dependable Computing."},{"key":"e_1_3_1_46_2","article-title":"Toward Hardware-Based IP Vulnerability Detection and Post-Deployment Patching in Systems-on-Chip","author":"Tan Benjamin","year":"2020","unstructured":"Benjamin Tan, Rana Elnaggar, Jason M. Fung, Ramesh Karri, and Krishnendu Chakrabarty. 2020. Toward Hardware-Based IP Vulnerability Detection and Post-Deployment Patching in Systems-on-Chip. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2020).","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"e_1_3_1_47_2","article-title":"Saca-FI: A microarchitecture-level fault injection framework for reliability analysis of systolic array based CNN accelerator","author":"Tan Jingweijia","year":"2023","unstructured":"Jingweijia Tan, Qixiang Wang, Kaige Yan, Xiaohui Wei, and Xin Fu. 2023. Saca-FI: A microarchitecture-level fault injection framework for reliability analysis of systolic array based CNN accelerator. Future Generation Computer Systems (2023).","journal-title":"Future Generation Computer Systems"},{"key":"e_1_3_1_48_2","volume-title":"Proceedings of the IEEE International Conference on Computer Design","author":"Vacca Eleonora","year":"2023","unstructured":"Eleonora Vacca, Giorgio Ajmone, and Luca Sterpone. 2023. RunSAFER: A novel runtime fault detection approach for systolic array accelerators. In Proceedings of the IEEE International Conference on Computer Design."},{"key":"e_1_3_1_49_2","volume-title":"Proceedings of the International SoC Design Conference","author":"Venkataramanaiah Shreyas K.","year":"2020","unstructured":"Shreyas K. Venkataramanaiah, Shihui Yin, Yu Cao, and Jae-Sun Seo. 2020. Deep neural network training accelerator designs in ASIC and FPGA. In Proceedings of the International SoC Design Conference."},{"key":"e_1_3_1_50_2","volume-title":"Proceedings of the ACM\/IEEE Design Automation Conference","author":"Yang Lei","year":"2020","unstructured":"Lei Yang, Zheyu Yan, Meng Li, Hyoukjun Kwon, Liangzhen Lai, Tushar Krishna, Vikas Chandra, Weiwen Jiang, and Yiyu Shi. 2020. Co-exploration of neural architectures and heterogeneous ASIC accelerator designs targeting multiple tasks. In Proceedings of the ACM\/IEEE Design Automation Conference."},{"key":"e_1_3_1_51_2","unstructured":"Wenpeng Yin Katharina Kann Mo Yu and Hinrich Sch\u00fctze. 2017. Comparative study of CNN and RNN for natural language processing. arXiv:1702.01923. Retrieved from https:\/\/arxiv.org\/abs\/1702.01923"},{"key":"e_1_3_1_52_2","article-title":"Fault-tolerant systolic array based accelerators for deep neural network execution","author":"Zhang Jeff Jun","year":"2019","unstructured":"Jeff Jun Zhang, Kanad Basu, and Siddharth Garg. 2019. Fault-tolerant systolic array based accelerators for deep neural network execution. IEEE Design and Test (2019).","journal-title":"IEEE Design and Test"},{"key":"e_1_3_1_53_2","volume-title":"Proceedings of the IEEE VLSI Test Symposium","author":"Zhang Jeff Jun","year":"2018","unstructured":"Jeff Jun Zhang, Tianyu Gu, Kanad Basu, and Siddharth Garg. 2018. Analyzing and mitigating the impact of permanent faults on a systolic array based neural network accelerator. In Proceedings of the IEEE VLSI Test Symposium."},{"key":"e_1_3_1_54_2","volume-title":"Proceedings of the IEEE International Conference on Computer Design.","author":"Zhao Yingnan","year":"2022","unstructured":"Yingnan Zhao, Ke Wang, and Ahmed Louri. 2022. FSA: An efficient fault-tolerant systolic array-based DNN accelerator architecture. In Proceedings of the IEEE International Conference on Computer Design."}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3770920","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,11,11]],"date-time":"2025-11-11T13:50:20Z","timestamp":1762869020000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3770920"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,11,11]]},"references-count":53,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2026,1,31]]}},"alternative-id":["10.1145\/3770920"],"URL":"https:\/\/doi.org\/10.1145\/3770920","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"value":"1084-4309","type":"print"},{"value":"1557-7309","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,11,11]]},"assertion":[{"value":"2025-05-21","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2025-09-28","order":2,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2025-11-11","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}