{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,14]],"date-time":"2026-07-14T12:21:30Z","timestamp":1784031690723,"version":"3.55.0"},"reference-count":34,"publisher":"Association for Computing Machinery (ACM)","issue":"4","funder":[{"name":"NSF","award":["CNS-2453370"],"award-info":[{"award-number":["CNS-2453370"]}]},{"name":"Villanova College of Engineering Last Year Ph.D. Fellowship"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2025,12,31]]},"abstract":"<jats:p>\n                    The advent of quantum computing poses a significant threat to modern cryptography. To address this challenge, the\n                    <jats:bold>National Institute of Standards and Technology (NIST)<\/jats:bold>\n                    has initiated the\n                    <jats:bold>Post-Quantum Cryptography (PQC)<\/jats:bold>\n                    standardization process, and several algorithms have been selected (a few are still under consideration in the additional standardization process). Among these schemes, lattice-based PQC has emerged as a promising approach and garnered substantial attention from the implementation community, especially on the hardware platforms. Notably, the\n                    <jats:bold>Field-Programmable Gate Array (FPGA)<\/jats:bold>\n                    has gained considerable attention as a convenient platform for hardware implementation, not only from NIST but also from the research community, as reflected by the related recommendations from NIST and the number of works reported recently.\n                  <\/jats:p>\n                  <jats:p>\n                    This work follows the existing trend of developing novel FPGA implementations for PQC. It is worth mentioning that the polynomial multiplication in these NIST lattice-based PQC algorithms can be implemented with\n                    <jats:bold>Number Theoretic Transform (NTT)<\/jats:bold>\n                    for efficiency. Nevertheless, there remains a lack of novel and universal NTT methods for polynomial multiplication at different sizes. For instance, for\n                    <jats:inline-formula content-type=\"math\/tex\">\n                      <jats:tex-math notation=\"LaTeX\" version=\"MathJax\">\\(n=512\\)<\/jats:tex-math>\n                    <\/jats:inline-formula>\n                    (F\n                    <jats:sc>alcon<\/jats:sc>\n                    and HAWK), the existing works are mostly limited to the Radix-2 NTT (other methods like Radix-4 or Radix-8 cannot be directly applied). To fill the research gap, this article presents a novel design framework, i.e.,\n                    <jats:bold>Efficient Mixed-RadIx NTT hardware accElerators for NIST post-quantuM cryptography (EMINEM)<\/jats:bold>\n                    , specially tailored for targeted schemes. Our design leverages Radix-4 for polynomial sizes of 256 and 1,024, while introducing a hybrid Radix-2\/4 strategy for NTT of length 512 and achieving comparable performance to pure Radix-4 at other lengths. In total, our contributions include: (i) a generic Radix-4\/Mixed-Radix NTT algorithm is proposed for\n                    <jats:inline-formula content-type=\"math\/tex\">\n                      <jats:tex-math notation=\"LaTeX\" version=\"MathJax\">\\(n=256\\)<\/jats:tex-math>\n                    <\/jats:inline-formula>\n                    , 512, and 1,024; (ii) an efficient NTT hardware accelerator is designed with the help of a new memory access pattern and some optimization techniques; (iii) two types of butterfly architectures are developed to obtain pure Radix-4 time complexity and low resource usage, respectively; (iv) a detailed implementation and comparison showcase the superior performance of the proposed design strategy. Overall, the proposed strategy enables the efficient deployment of Mixed-Radix NTT in targeted NIST schemes, surpassing the limitations of the conventional Radix-2 approach for 512-length NTT designs. The proposed design offers a significant advancement in the field, facilitating efficient FPGA acceleration of PQC standards.\n                  <\/jats:p>","DOI":"10.1145\/3771287","type":"journal-article","created":{"date-parts":[[2025,10,9]],"date-time":"2025-10-09T14:02:19Z","timestamp":1760018539000},"page":"1-25","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["EMINEM: Efficient FPGA Implementation of Mixed-RadIx NTT Hardware AccElerators for NIST Post-QuantuM Cryptography F\n                    <scp>alcon<\/scp>\n                    , Dilithium, and HAWK"],"prefix":"10.1145","volume":"18","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-1624-9500","authenticated-orcid":false,"given":"Yazheng","family":"Tu","sequence":"first","affiliation":[{"name":"Department of Electrical and Computer Engineering, Villanova University, Villanova, Pennsylvania, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4814-1318","authenticated-orcid":false,"given":"Jiafeng","family":"Xie","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Villanova University, Villanova, Pennsylvania, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2025,12,4]]},"reference":[{"key":"e_1_3_1_2_2","unstructured":"CRYSTALS Team. 2021. Dilithium. Retrieved from https:\/\/pq-crystals.org\/dilithium\/"},{"key":"e_1_3_1_3_2","unstructured":"Falcon. 2022. Fast Fourier Lattice-Based Compact Signatures over NTRU (Falcon). Retrieved from https:\/\/falcon-sign.info\/"},{"key":"e_1_3_1_4_2","doi-asserted-by":"crossref","unstructured":"Utsav Banerjee Tenzin S. Ukyab and Anantha P. Chandrakasan. 2019. Sapphire: A configurable crypto-processor for post-quantum lattice-based protocols (extended version). Paper 2019\/1140. Cryptology ePrint Archive. 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Retrieved from https:\/\/csrc.nist.gov\/pubs\/fips\/204\/final"},{"key":"e_1_3_1_10_2","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8715173"},{"key":"e_1_3_1_11_2","doi-asserted-by":"publisher","DOI":"10.1145\/1464291.1464352"},{"key":"e_1_3_1_12_2","doi-asserted-by":"publisher","DOI":"10.1145\/1464291.1464352"},{"key":"e_1_3_1_13_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.jsc.2013.09.002"},{"key":"e_1_3_1_14_2","unstructured":"HAWK. 2025. HAWK: A Signature Scheme Inspired by the Lattice Isomorphism Problem. Retrieved from https:\/\/hawk-sign.info\/"},{"key":"e_1_3_1_15_2","unstructured":"CRYSTALS Team. 2022. Kyber. Retrieved from https:\/\/pq-crystals.org\/kyber\/index.shtml"},{"key":"e_1_3_1_16_2","first-page":"210","volume-title":"Proceedings of the International Conference on Smart Card Research and Advanced Applications","author":"Land Georg","year":"2021","unstructured":"Georg Land, Pascal Sasdrich, and Tim G\u00fcneysu. 2021. A hard crystal-implementing Dilithium on reconfigurable hardware. In Proceedings of the International Conference on Smart Card Research and Advanced Applications. Springer, 210\u2013230."},{"key":"e_1_3_1_17_2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2023.3312423"},{"key":"e_1_3_1_18_2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2922999"},{"key":"e_1_3_1_19_2","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID60093.2024.00082"},{"key":"e_1_3_1_20_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2020.3017930"},{"key":"e_1_3_1_21_2","unstructured":"NIST PQC Forum. 2025. On Recommended Hardware. Retrieved from https:\/\/groups.google.com\/a\/list.nist.gov\/g\/pqc-forum\/c\/cJxMq0_90gU\/m\/qbGEs3TXGwAJ"},{"key":"e_1_3_1_22_2","doi-asserted-by":"publisher","DOI":"10.1090\/S0025-5718-1971-0301966-0"},{"key":"e_1_3_1_23_2","unstructured":"National Institute of Standards and Technology. 2024. Post-Quantum Cryptography: Additional Digital Signature Schemes. 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