{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,1]],"date-time":"2026-06-01T18:26:43Z","timestamp":1780338403304,"version":"3.54.1"},"reference-count":30,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2026,12,2]],"date-time":"2026-12-02T00:00:00Z","timestamp":1796169600000},"content-version":"vor","delay-in-days":366,"URL":"http:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CF-2218845, ECCS-2229472, ECCS-232901"],"award-info":[{"award-number":["CF-2218845, ECCS-2229472, ECCS-232901"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000181","name":"Air Force Office of Scientific Research","doi-asserted-by":"publisher","award":["FA9550- 23-1-0261"],"award-info":[{"award-number":["FA9550- 23-1-0261"]}],"id":[{"id":"10.13039\/100000181","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000185","name":"Defense Advanced Research Projects Agency","doi-asserted-by":"publisher","award":["D25AC00374-00"],"award-info":[{"award-number":["D25AC00374-00"]}],"id":[{"id":"10.13039\/100000185","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000006","name":"Office of Naval Research","doi-asserted-by":"publisher","award":["N00014-23-1-2221"],"award-info":[{"award-number":["N00014-23-1-2221"]}],"id":[{"id":"10.13039\/100000006","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100003529","name":"European Union Agency for Cybersecurity","doi-asserted-by":"publisher","award":["PE00000014"],"award-info":[{"award-number":["PE00000014"]}],"id":[{"id":"10.13039\/501100003529","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["Proc. ACM Meas. Anal. Comput. Syst."],"published-print":{"date-parts":[[2025,12]]},"abstract":"<jats:p>Despite growing interest in virtualization of Field-Programmable Gate Arrays (FPGAs), existing approaches predominantly target datacenter-class FPGAs, which heavily rely on external (powerful) servers for hypervisor execution and resource management. This significantly limits their suitability for edge environments where autonomy, energy efficiency, and direct low-latency access to physical Input\/Output (I\/O) are critical. To address this goal, this paper introduces \u00b5-VF, a lightweight virtualization framework specifically designed to enable robust multi-tenancy on embedded FPGAs operating autonomously at the network edge. \u00b5-VF embeds all virtualization logic entirely onboard the FPGA unit, eliminating the need for any off-chip infrastructure and thus significantly reducing overall system power consumption. Each tenant operates within a secure and isolated container on the on-chip Processing System (PS), coupled with exclusive access to a dedicated Programmable Logic (PL) region. Additionally, \u00b5-VF fully virtualizes external General-Purpose Input\/Output (GPIO) directly within the PL fabric, thus enabling independent, concurrent and latency-sensitive access to shared peripherals. We have implemented a prototype of \u00b5-VF with a Zynq UltraScale+ ZCU102 board with PL operating at 100 MHz. Experimental results demonstrate that the hardware virtualization layer utilizes less than 10% of the FPGA's logic resources, with 85% available for tenant applications compared to 50% in prior work. Moreover, \u00b5-VF adds 2.93% to Memory-Mapped I\/O (MMIO) access latency compared to native execution for single-tenant operation, increasing to 6.5% with four concurrent tenants. Memory throughput measurements show 1.8% overhead for write operations and negligible impact on read operations, with aggregate throughput 17.1% higher than previous frameworks. Hardware-based GPIO remapping completes in 20 nanoseconds.<\/jats:p>","DOI":"10.1145\/3771581","type":"journal-article","created":{"date-parts":[[2025,12,2]],"date-time":"2025-12-02T20:07:03Z","timestamp":1764706023000},"page":"1-26","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["\u00b5-VF: Enabling Virtualization of Embedded FPGAs"],"prefix":"10.1145","volume":"9","author":[{"ORCID":"https:\/\/orcid.org\/0009-0008-0837-4070","authenticated-orcid":false,"given":"Vincenzo Alessio","family":"Bucaria","sequence":"first","affiliation":[{"name":"University of Messina, Messina, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6299-140X","authenticated-orcid":false,"given":"Francesco","family":"Longo","sequence":"additional","affiliation":[{"name":"University of Messina, Messina, Italy and CINI: National Interuniversity Consortium for Informatics, Rome, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1469-7860","authenticated-orcid":false,"given":"Giovanni","family":"Merlino","sequence":"additional","affiliation":[{"name":"University of Messina, Messina, Italy and CINI: National Interuniversity Consortium for Informatics, Rome, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4999-4507","authenticated-orcid":false,"given":"Francesco","family":"Restuccia","sequence":"additional","affiliation":[{"name":"Northeastern University, Boston, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2025,12,2]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASET.2017.7983723"},{"key":"e_1_2_1_2_1","volume-title":"Retrieved","author":"Xilinx AMD","year":"2023","unstructured":"AMD Xilinx. 2023. DFX Decoupler v1.0 LogiCORE IP Product Guide. https:\/\/docs.amd.com\/r\/en-US\/pg375-dfx-decoupler. Retrieved July 30, 2025 from https:\/\/docs.amd.com\/r\/en-US\/pg375-dfx-decoupler PG375."},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/3506713"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2012.25"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","unstructured":"Ignacio Bravo-Mu\u00f1oz Alfredo Gardel-Vicente and Jos\u00e9 Luis L\u00e1zaro-Galilea. 2020. New Applications and Architectures Based on FPGA\/SoC. doi:10.3390\/electronics9111789","DOI":"10.3390\/electronics9111789"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2014.42"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/3530775"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/NCA.2012.38"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/3713078"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/SBCCI62366.2024.10704009"},{"key":"e_1_2_1_11_1","first-page":"107","volume-title":"13th USENIX Symposium on Operating Systems Design and Implementation (OSDI 18)","author":"Khawaja Ahmed","unstructured":"Ahmed Khawaja, Joshua Landgraf, Rohith Prakash, Michael Wei, Eric Schkufza, and Christopher J. Rossbach. 2018. Sharing, Protection, and Compatibility for Reconfigurable Fabric with AmorphOS. In 13th USENIX Symposium on Operating Systems Design and Implementation (OSDI 18). USENIX Association, Carlsbad, CA, 107-127. http:\/\/www.usenix.org\/conference\/osdi18\/presentation\/khawaja"},{"key":"e_1_2_1_12_1","first-page":"991","volume-title":"14th USENIX Symposium on Operating Systems Design and Implementation (OSDI 20)","author":"Korolija Dario","year":"2020","unstructured":"Dario Korolija, Timothy Roscoe, and Gustavo Alonso. 2020. Do OS abstractions make sense on FPGAs?. In 14th USENIX Symposium on Operating Systems Design and Implementation (OSDI 20). USENIX Association, 991-1010. https:\/\/www.usenix.org\/conference\/osdi20\/presentation\/roscoe"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/3373376.3378482"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/CLOUD.2018.00122"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/3284357"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/3648475"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/2990299.2990301"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/ESARS-ITEC57127.2023.10114808"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/2628194.2628195"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/MS.2015.43"},{"key":"e_1_2_1_21_1","volume-title":"Smith and Alex Zamfirescu","author":"Douglas","year":"1998","unstructured":"Douglas J. Smith and Alex Zamfirescu. 1998. HDL Chip Design: A Practical Guide for Designing, Synthesizing and Simulating ASICs and FPGAs Using VHDL or Verilog. Doone Publications."},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/TSUSC.2023.3273852"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/MCOM.2018.1701047"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2018.00031"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/3405794"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2019.05.003"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.23919\/FPL.2017.8056807"},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/3373376.3378491"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA52012.2021.00044"},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/3124680.3124743"}],"container-title":["Proceedings of the ACM on Measurement and Analysis of Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3771581","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3771581","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,12,3]],"date-time":"2025-12-03T17:26:10Z","timestamp":1764782770000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3771581"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,12]]},"references-count":30,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2025,12]]}},"alternative-id":["10.1145\/3771581"],"URL":"https:\/\/doi.org\/10.1145\/3771581","relation":{},"ISSN":["2476-1249"],"issn-type":[{"value":"2476-1249","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,12]]},"assertion":[{"value":"2025-12-02","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}