{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,9]],"date-time":"2026-06-09T15:21:50Z","timestamp":1781018510904,"version":"3.54.1"},"reference-count":36,"publisher":"Association for Computing Machinery (ACM)","issue":"2","content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2026,3,31]]},"abstract":"<jats:p>\n                    Modern embedded control applications in\n                    <jats:italic toggle=\"yes\">Cyber-Physical Systems<\/jats:italic>\n                    (CPSs) often have complex inter-dependencies in their functionalities and are hence represented as Directed-Acyclic Task Graphs (DTGs). To meet complex performance as well as deployment-related logistic constraints, these applications may need to be implemented on a distributed and heterogeneous platform. Many-a-times, it becomes necessary to dynamically run a new application like say,\n                    <jats:italic toggle=\"yes\">an alarm service routine<\/jats:italic>\n                    , on an already operational platform, where pre-existing workloads consisting of other application tasks along with their messages are running. However, although there is a significant body of literature dealing with the static scheduling of DTGs on different types of platforms, to the best of our knowledge, there does not exist any prominent work for the dynamic scheduling of dynamically arriving DTG applications on an already preoccupied platform. The primary reason for this dearth in strategies may be attributed to the inherent design as well as computational complexity associated with the\n                    <jats:italic toggle=\"yes\">dynamic inclusion of a new DTG application by effectively reclaiming the free slots within an already existing schedule. While delivering quick response times to the dynamically arrived application, the newly generated schedule must also ensure that it does not ever cause deadline violations for the already running applications<\/jats:italic>\n                    . This work proposes a novel makespan-minimizing scheduling algorithm called\n                    <jats:italic toggle=\"yes\">DTG Scheduler for Preloaded Platforms<\/jats:italic>\n                    (\n                    <jats:italic toggle=\"yes\">DSPP<\/jats:italic>\n                    ).\n                    <jats:italic toggle=\"yes\">DSPP<\/jats:italic>\n                    is an efficient list-based heuristic strategy for co-scheduling the tasks as well as the inter-task messages of a DTG structured application on preloaded heterogeneous processing elements, interconnected via shared buses. The effectiveness of\n                    <jats:italic toggle=\"yes\">DSPP<\/jats:italic>\n                    has been meticulously examined through simulation, employing benchmark DTGs for evaluation. The conducted experiments reveal the generic efficacy of\n                    <jats:italic toggle=\"yes\">DSPP<\/jats:italic>\n                    across an extensive set of considered test case scenarios. Extensive simulation results show that\n                    <jats:italic toggle=\"yes\">DSPP<\/jats:italic>\n                    can achieve up to \u223c13% reduction in makespan in the best case and \u223c10% on average, outperforming existing state-of-the-art methods.\n                  <\/jats:p>","DOI":"10.1145\/3772003","type":"journal-article","created":{"date-parts":[[2025,10,21]],"date-time":"2025-10-21T11:34:41Z","timestamp":1761046481000},"page":"1-29","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["Scheduling Task Graph Applications on Preloaded Shared-Bus based Heterogeneous Platforms"],"prefix":"10.1145","volume":"31","author":[{"ORCID":"https:\/\/orcid.org\/0009-0004-5758-8279","authenticated-orcid":false,"given":"Chhavi","family":"Chaudhary","sequence":"first","affiliation":[{"name":"Department of Artificial Intelligence, Indian Institute of Technology Kharagpur","place":["Kharagpur, India"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4481-102X","authenticated-orcid":false,"given":"Rajesh","family":"Devaraj","sequence":"additional","affiliation":[{"name":"SW TEGRA, Nvidia Graphics","place":["Bangalore, India"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5930-2180","authenticated-orcid":false,"given":"Arnab","family":"Sarkar","sequence":"additional","affiliation":[{"name":"Advanced Technology Development Centre, Indian Institute of Technology Kharagpur","place":["Kharagpur, India"]}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2025,12,17]]},"reference":[{"key":"e_1_3_2_2_2","doi-asserted-by":"publisher","DOI":"10.1145\/2968478.2968490"},{"key":"e_1_3_2_3_2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-08696-5"},{"key":"e_1_3_2_4_2","doi-asserted-by":"publisher","DOI":"10.1109\/RAM.2018.8463048"},{"key":"e_1_3_2_5_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2019.101706"},{"key":"e_1_3_2_6_2","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2016.2526682"},{"key":"e_1_3_2_7_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2957374"},{"key":"e_1_3_2_8_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2011.200"},{"key":"e_1_3_2_9_2","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2014.2308175"},{"key":"e_1_3_2_10_2","doi-asserted-by":"publisher","DOI":"10.1145\/2660496"},{"key":"e_1_3_2_11_2","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2010.204"},{"key":"e_1_3_2_12_2","doi-asserted-by":"publisher","DOI":"10.3390\/su142416539"},{"key":"e_1_3_2_13_2","doi-asserted-by":"publisher","DOI":"10.1109\/TVT.2020.2995146"},{"key":"e_1_3_2_14_2","doi-asserted-by":"publisher","DOI":"10.1109\/CCDC62350.2024.10587381"},{"key":"e_1_3_2_15_2","doi-asserted-by":"publisher","DOI":"10.1145\/3610300"},{"key":"e_1_3_2_16_2","doi-asserted-by":"publisher","DOI":"10.1002\/spe.2802"},{"key":"e_1_3_2_17_2","doi-asserted-by":"publisher","DOI":"10.1109\/71.481597"},{"key":"e_1_3_2_18_2","doi-asserted-by":"publisher","DOI":"10.1002\/cpe.5987"},{"key":"e_1_3_2_19_2","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2013.57"},{"key":"e_1_3_2_20_2","doi-asserted-by":"publisher","DOI":"10.1109\/71.993206"},{"key":"e_1_3_2_21_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.jpdc.2015.04.005"},{"key":"e_1_3_2_22_2","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2020.3041829"},{"key":"e_1_3_2_23_2","doi-asserted-by":"publisher","DOI":"10.1145\/3715323"},{"key":"e_1_3_2_24_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.parco.2021.102828"},{"key":"e_1_3_2_25_2","doi-asserted-by":"publisher","DOI":"10.1007\/s40747-021-00528-1"},{"key":"e_1_3_2_26_2","doi-asserted-by":"publisher","DOI":"10.1007\/s11227-022-04703-0"},{"key":"e_1_3_2_27_2","doi-asserted-by":"publisher","DOI":"10.1007\/s11227-023-05806-y"},{"key":"e_1_3_2_28_2","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2013.57"},{"key":"e_1_3_2_29_2","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2016.2573598"},{"key":"e_1_3_2_30_2","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2005.64"},{"key":"e_1_3_2_31_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2021.3059569"},{"key":"e_1_3_2_32_2","unstructured":"IBM. 2024. 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