{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,13]],"date-time":"2026-04-13T23:16:18Z","timestamp":1776122178484,"version":"3.50.1"},"reference-count":42,"publisher":"Association for Computing Machinery (ACM)","issue":"2","funder":[{"DOI":"10.13039\/501100001809","name":"Natural Science Foundation of China","doi-asserted-by":"crossref","award":["62220106011"],"award-info":[{"award-number":["62220106011"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"crossref"}]},{"name":"State Key Laboratory of Radio Frequency Heterogeneous Integration","award":["2025003"],"award-info":[{"award-number":["2025003"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2026,3,31]]},"abstract":"<jats:p>\n                    Routing congestion prediction expedites the closure of FPGA placement and routing (PnR). Current prediction methods employ convolutional models, taking advantage of their capacity of dealing with image-style inputs. However, these methods neglect the direct representation of circuit netlist and its information fusion with placement scheme. Moreover, the limited size of the convolutional kernel struggles to capture circuit connectivity in distant geometric regions. To address these issues, this article presents a graph-based routing congestion prediction framework that fuses the information contained in the circuit\u2019s topological netlist and geometric placement scheme, and leverages a conditional generative adversarial network (cGAN) model to achieve optimized prediction performance compared to contemporary approaches. Our framework encompasses three key components: (1) the HeteroGraph, a heterogeneous graph that integrates a netlist subgraph and a layout subgraph by space mapping edges; (2) the HeteroGNN, a heterogeneous graph neural network that learns the latent features of both the circuit netlist and placement scheme through dual-space message-passing; and (3) the HeteroGNN-embedded cGAN, a model that combines the HeteroGNN with a cGAN for accurate FPGA routing congestion prediction. Compared to state-of-the-art approaches, our method reduces the routing congestion prediction\u2019s root-mean-square error by 18.2% on the VTR7 benchmarks and by 15.0% on the large-scale Titan23 benchmarks. The code associated with this article can be found at\n                    <jats:ext-link xmlns:xlink=\"http:\/\/www.w3.org\/1999\/xlink\" xlink:href=\"https:\/\/github.com\/AIPnR\/FPGA_Hetero_Congestion_Prediction\">https:\/\/github.com\/AIPnR\/FPGA_Hetero_Congestion_Prediction<\/jats:ext-link>\n                    .\n                  <\/jats:p>","DOI":"10.1145\/3773770","type":"journal-article","created":{"date-parts":[[2025,10,25]],"date-time":"2025-10-25T10:58:43Z","timestamp":1761389923000},"page":"1-24","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["FPGA Routing Congestion Prediction via Graph Learning-Aided Conditional GAN"],"prefix":"10.1145","volume":"31","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-9375-0457","authenticated-orcid":false,"given":"Qingyu","family":"Yang","sequence":"first","affiliation":[{"name":"College of Computer Science and Software Engineering, Shenzhen University","place":["Shenzhen, China"]},{"name":"School of Computer Science, University of Nottingham Ningbo China","place":["Shenzhen, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7248-5180","authenticated-orcid":false,"given":"Jingjin","family":"Li","sequence":"additional","affiliation":[{"name":"School of Computer Science, University of Nottingham Ningbo China","place":["Ningbo, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2953-9742","authenticated-orcid":false,"given":"Rui","family":"Li","sequence":"additional","affiliation":[{"name":"School of Information Science and Technology, ShanghaiTech University","place":["Shanghai, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1018-1912","authenticated-orcid":false,"given":"Yuting","family":"He","sequence":"additional","affiliation":[{"name":"School of Computer Science, University of Nottingham Ningbo China","place":["Ningbo, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4244-5916","authenticated-orcid":false,"given":"Yajun","family":"Ha","sequence":"additional","affiliation":[{"name":"School of Information Science and Technology, ShanghaiTech University","place":["Shanghai, China"]},{"name":"Shanghai Engineering Research Center of Energy Efficient and Custom AI IC, ShanghaiTech University","place":["Shanghai, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1420-0815","authenticated-orcid":false,"given":"Linlin","family":"Shen","sequence":"additional","affiliation":[{"name":"School of Artificial Intelligence, Shenzhen University","place":["Shenzhen, China"]},{"name":"The State Key Laboratory of Radio Frequency Heterogeneous Integration, Shenzhen University","place":["Shenzhen, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1722-568X","authenticated-orcid":false,"given":"Ruibin","family":"Bai","sequence":"additional","affiliation":[{"name":"School of Computer Science, University of Nottingham Ningbo China","place":["Ningbo, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0305-2135","authenticated-orcid":false,"given":"Heng","family":"Yu","sequence":"additional","affiliation":[{"name":"School of Computer Science, University of Nottingham Ningbo China","place":["Ningbo, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2025,12,17]]},"reference":[{"key":"e_1_3_2_2_2","doi-asserted-by":"publisher","DOI":"10.1109\/ASP-DAC47756.2020.9045178"},{"key":"e_1_3_2_3_2","first-page":"59","volume-title":"ACM\/SIGDA 7th International Symposium on Field Programmable Gate Arrays","author":"Betz V.","year":"1999","unstructured":"V. Betz and J. Rose. 1999. FPGA routing architecture: Segmentation and buffering to optimize speed and density. In ACM\/SIGDA 7th International Symposium on Field Programmable Gate Arrays. 59\u201368."},{"issue":"2","key":"e_1_3_2_4_2","doi-asserted-by":"crossref","first-page":"4","DOI":"10.1109\/MCAS.2021.3071607","article-title":"FPGA architecture: Principles and progression","volume":"21","author":"Boutros A.","year":"2021","unstructured":"A. Boutros and V. Betz. 2021. FPGA architecture: Principles and progression. IEEE Circuits and Systems Magazine 21, 2 (2021), 4\u201329.","journal-title":"IEEE Circuits and Systems Magazine"},{"issue":"10","key":"e_1_3_2_5_2","doi-asserted-by":"crossref","first-page":"2022","DOI":"10.1109\/TCAD.2017.2778058","article-title":"RippleFPGA: Routability-driven simultaneous packing and placement for modern FPGAs","volume":"37","year":"2018","unstructured":"G. Chen, C.-W. Pui, W.-K. Chow, K.-C. Lam, J. Kuang, and E. F. Y. Young. 2018. RippleFPGA: Routability-driven simultaneous packing and placement for modern FPGAs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37, 10 (2018), 2022\u20132035.","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"issue":"1","key":"e_1_3_2_6_2","first-page":"164","article-title":"PROS 2.0: A plug-in for routability optimization and routed wirelength estimation using deep learning","volume":"42","year":"2022","unstructured":"J. Chen, J. Kuang, G. Zhao, D. J.-H. Huang, and E. F. Y. Young. 2022. PROS 2.0: A plug-in for routability optimization and routed wirelength estimation using deep learning. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 42, 1 (2022), 164\u2013177.","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"e_1_3_2_7_2","first-page":"914","volume-title":"IEEE\/ACM International Conference on Computer-Aided Design","author":"Chen S.-C.","year":"2017","unstructured":"S.-C. Chen and Y.-W. Chang. 2017. FPGA placement and routing. In IEEE\/ACM International Conference on Computer-Aided Design. 914\u2013921."},{"issue":"2","key":"e_1_3_2_8_2","first-page":"564","article-title":"Detailed routing short violation prediction using graph-based deep learning model","volume":"69","year":"2022","unstructured":"X. Chen, Z. Di, W. Wu, Q. Wu, J. Shi, and Q. Feng. 2022. Detailed routing short violation prediction using graph-based deep learning model. IEEE Transactions on Circuits and Systems II: Express Briefs 69, 2 (2022), 564\u2013568.","journal-title":"IEEE Transactions on Circuits and Systems II: Express Briefs"},{"key":"e_1_3_2_9_2","first-page":"12873","volume-title":"IEEE\/CVF Conference on Computer Vision and Pattern Recognition","author":"Esser P.","year":"2021","unstructured":"P. Esser, R. Rombach, and B. Ommer. 2021. Taming transformers for high-resolution image synthesis. In IEEE\/CVF Conference on Computer Vision and Pattern Recognition. 12873\u201312883."},{"key":"e_1_3_2_10_2","doi-asserted-by":"crossref","unstructured":"H. Gu J. Gu K. Peng J. Chen J. Yang and Z. Zhu. 2025. Routability-driven macro placement engine for modern FPGAs with complex cascade shape and region constraints. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 44 11 (2025) 4381\u20134394.","DOI":"10.1109\/TCAD.2025.3562952"},{"key":"e_1_3_2_11_2","article-title":"Graph Representation Learning","author":"Hamilton W. L.","year":"2020","unstructured":"W. L. Hamilton. 2020. Graph Representation Learning. Retrieved October 25, 2024 from https:\/\/cs.mcgill.ca\/ wlh\/comp766\/files\/chapter4_draft_mar29.pdf","journal-title":"Retrieved October 25, 2024 from https:\/\/cs.mcgill.ca\/ wlh\/comp766\/files\/chapter4_draft_mar29.pdf"},{"issue":"5","key":"e_1_3_2_12_2","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/3451179","article-title":"Machine learning for electronic design automation: A survey","volume":"26","year":"2021","unstructured":"G. Huang, J. Hu, Y. He, J. Liu, M. Ma, Z. Shen, J. Wu, Y. Xu, H. Zhang, K. Zhong, X. Ning, Y. Ma, H. Yang, B. Yu, H. Yang, and Y. Wang. 2021. Machine learning for electronic design automation: A survey. ACM Transactions on Design Automation of Electronic Systems 26, 5 (2021), 1\u201346.","journal-title":"ACM Transactions on Design Automation of Electronic Systems"},{"issue":"9","key":"e_1_3_2_13_2","doi-asserted-by":"crossref","first-page":"1425","DOI":"10.1109\/TVLSI.2023.3271932","article-title":"DRC violation prediction after global route through convolutional neural network","volume":"31","year":"2023","unstructured":"W.-T. Hung, Y.-G. Chen, J.-G. Lin, Y.-W. Yang, C.-H. Tsai, and M. C.-T. Chao. 2023. DRC violation prediction after global route through convolutional neural network. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 31, 9 (2023), 1425\u20131438.","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"key":"e_1_3_2_14_2","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2017.632"},{"key":"e_1_3_2_15_2","article-title":"ISPD 2016 routability-driven fpga placement contest","year":"2016","unstructured":"ISPD. 2016. ISPD 2016 routability-driven fpga placement contest. Retrieved October 25, 2024 from https:\/\/ispd.cc\/contests\/16\/ispd2016_contest.html","journal-title":"Retrieved October 25, 2024 from https:\/\/ispd.cc\/contests\/16\/ispd2016_contest.html"},{"key":"e_1_3_2_16_2","first-page":"217","volume-title":"27th International Conference on Very Large Scale Integration","author":"Kirby R.","year":"2019","unstructured":"R. Kirby, S. Godil, R. Roy, and B. Catanzaro. 2019. CongestionNet: Routing congestion prediction using deep graph neural networks. In 27th International Conference on Very Large Scale Integration. 217\u2013222."},{"issue":"2","key":"e_1_3_2_17_2","first-page":"791","article-title":"Refscat: Formal verification of logic-optimized multipliers via automated reference multiplier generation and sca-sat synergy","volume":"44","year":"2024","unstructured":"R. Li, L. Li, H. Yu, M. Fujita, W. Jiang, and Y. Ha. 2024. Refscat: Formal verification of logic-optimized multipliers via automated reference multiplier generation and sca-sat synergy. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 44, 2 (2024), 791\u2013804.","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"e_1_3_2_18_2","volume-title":"Introduction to Graph Neural Networks","author":"Liu Z.","year":"2022","unstructured":"Z. Liu and J. Zhou. 2022. Introduction to Graph Neural Networks. Springer Nature."},{"issue":"2","key":"e_1_3_2_19_2","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/3636461","article-title":"GAN-place: Advancing open source placers to commercial-quality using generative adversarial networks and transfer learning","volume":"29","author":"Lu Y.-C.","year":"2024","unstructured":"Y.-C. Lu, H. Ren, H.-H. Hsiao, and S. K. Lim. 2024. GAN-place: Advancing open source placers to commercial-quality using generative adversarial networks and transfer learning. ACM Transactions on Design Automation of Electronic Systems 29, 2 (2024), 1\u201317.","journal-title":"ACM Transactions on Design Automation of Electronic Systems"},{"issue":"2","key":"e_1_3_2_20_2","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/2617593","article-title":"VTR 7.0: Next generation architecture and CAD system for FPGAs","volume":"7","year":"2014","unstructured":"J. Luu, J. Goeders, M. Wainberg, A. Somerville, T. Yu, K. Nasartschuk, M. Nasr, S. Wang, T. Liu, N. Ahmed, K. B. Kent, J. Anderson, J. Rose, and V. Betz. 2014. VTR 7.0: Next generation architecture and CAD system for FPGAs. ACM Transactions on Reconfigurable Technology and Systems 7, 2 (2014), 1\u201330.","journal-title":"ACM Transactions on Reconfigurable Technology and Systems"},{"key":"e_1_3_2_21_2","first-page":"1","volume-title":"IEEE 14th International Conference on ASIC","author":"Ma C.","year":"2021","unstructured":"C. Ma, Y. Xiao, S. Wang, J. Yu, and J. Chen. 2021. CongestNN: An Bi-directional congestion prediction framework for large-scale heterogeneous FPGAs. In IEEE 14th International Conference on ASIC. 1\u20134."},{"key":"e_1_3_2_22_2","first-page":"427","volume-title":"28th International Conference on Field Programmable Logic and Applications","year":"2018","unstructured":"D. Maarouf, A. Alhyari, Z. Abuowaimer, T. Martin, A. Gunter, and G. Grewal. 2018. Machine-learning based congestion estimation for modern FPGAs. In 28th International Conference on Field Programmable Logic and Applications. 427\u20134277."},{"key":"e_1_3_2_23_2","first-page":"138","volume-title":"30th International Conference on Field-Programmable Logic and Applications","author":"Maarouff D.","year":"2020","unstructured":"D. Maarouff, A. Shamli, T. Martin, G. Grewal, and S. Areibi. 2020. A deep-learning framework for predicting congestion during FPGA placement. In 30th International Conference on Field-Programmable Logic and Applications. 138\u2013144."},{"issue":"2","key":"e_1_3_2_24_2","doi-asserted-by":"crossref","first-page":"641","DOI":"10.1109\/TCAD.2023.3313101","article-title":"Multielectrostatic FPGA placement considering SLICEL\u2013SLICEM heterogeneity, clock feasibility, and timing optimization","volume":"43","author":"Mai J.","year":"2024","unstructured":"J. Mai, J. Wang, Z. Di, and Y. Lin. 2024. Multielectrostatic FPGA placement considering SLICEL\u2013SLICEM heterogeneity, clock feasibility, and timing optimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 43, 2 (2024), 641\u2013653.","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"e_1_3_2_25_2","unstructured":"M. Mirza and S. Osindero. 2014. Conditional generative adversarial nets. arXiv:1411.1784. Retrieved from https:\/\/arxiv.org\/abs\/1411.1784"},{"issue":"2","key":"e_1_3_2_26_2","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/3388617","article-title":"VTR 8: High-performance CAD and customizable FPGA architecture modelling","volume":"13","year":"2020","unstructured":"K. E. Murray, O. Petelin, S. Zhong, J. M. Wang, M. Eldafrawy, J.-P. Legault, E. Sha, A. G. Graham, J. Wu, M. J. P. Walker, H. Zeng, P. Patros, J. Luu, K. B. Kent, and V. Betz. 2020. VTR 8: High-performance CAD and customizable FPGA architecture modelling. ACM Transactions on Reconfigurable Technology and Systems 13, 2 (2020), 1\u201355.","journal-title":"ACM Transactions on Reconfigurable Technology and Systems"},{"key":"e_1_3_2_27_2","first-page":"1","volume-title":"23rd International Conference on Field programmable Logic and Applications","author":"Murray K. E.","year":"2013","unstructured":"K. E. Murray, S. Whitty, S. Liu, J. Luu, and V. Betz. 2013. Titan: Enabling large and complex benchmarks in academic cad. In 23rd International Conference on Field programmable Logic and Applications. 1\u20138."},{"key":"e_1_3_2_28_2","first-page":"929","volume-title":"IEEE\/ACM International Conference on Computer-Aided Design","author":"Pui C.-W.","year":"2017","unstructured":"C.-W. Pui, G. Chen, Y. Ma, E. F. Y. Young, and B. Yu. 2017. Clock-aware ultrascale FPGA placement with machine learning routability prediction. In IEEE\/ACM International Conference on Computer-Aided Design. 929\u2013936."},{"key":"e_1_3_2_29_2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-24574-4_28"},{"key":"e_1_3_2_30_2","first-page":"1","volume-title":"ACM SIGGRAPH Conference","year":"2022","unstructured":"C. Saharia, W. Chan, H. Chang, C. Lee, J. Ho, T. Salimans, D. Fleet, and M. Norouzi. 2022. Palette: Image-to-image diffusion models. In ACM SIGGRAPH Conference. 1\u201310."},{"issue":"2","key":"e_1_3_2_31_2","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/3543853","article-title":"A comprehensive survey on electronic design automation and graph neural networks: Theory and applications","volume":"28","author":"S\u00e1nchez D.","year":"2023","unstructured":"D. S\u00e1nchez, L. Servadei, G. N. Kiprit, R. Wille, and W. Ecker. 2023. A comprehensive survey on electronic design automation and graph neural networks: Theory and applications. ACM Transactions on Design Automation of Electronic Systems 28, 2 (2023), 1\u201327.","journal-title":"ACM Transactions on Design Automation of Electronic Systems"},{"issue":"1","key":"e_1_3_2_32_2","doi-asserted-by":"crossref","first-page":"61","DOI":"10.1109\/TNN.2008.2005605","article-title":"The graph neural network model","volume":"20","author":"Scarselli F.","year":"2009","unstructured":"F. Scarselli, M. Gori, A. C. Tsoi, M. Hagenbuchner, and G. Monfardini. 2009. The graph neural network model. IEEE Transactions on Neural Networks 20, 1 (2009), 61\u201380.","journal-title":"IEEE Transactions on Neural Networks"},{"key":"e_1_3_2_33_2","first-page":"1","volume-title":"Design, Automation and Test in Europe Conference and Exhibition","author":"Spindler P.","year":"2007","unstructured":"P. Spindler and F. M. Johannes. 2007. Fast and accurate routing demand estimation for efficient routability-driven placement. In Design, Automation and Test in Europe Conference and Exhibition. 1\u20136."},{"key":"e_1_3_2_34_2","doi-asserted-by":"crossref","unstructured":"H. Szentimrey A. Al-Hyari J. Foxcroft T. Martin D. Noel G. Grewal and S. Areibi. 2020. Machine learning for congestion management and routability prediction within FPGA placement. ACM Transactions on Design Automation of Electronic Systems 25 5 (2025) 1\u201325.","DOI":"10.1145\/3373269"},{"key":"e_1_3_2_35_2","unstructured":"A. Van Den Oord O. Vinyals and K. Kavukcuoglu. 2017. Neural discrete representation learning. In 31st International Conference on Neural Information Processing Systems 30 (2017) 6309\u2013 6318."},{"key":"e_1_3_2_36_2","article-title":"Verilog to Routing Architecture Files","year":"2020","unstructured":"VTR. 2020. Verilog to Routing Architecture Files. Retrieved October 25, 2024 from https:\/\/github.com\/verilog-to-routing\/vtr-verilog-to-routing\/tree\/master\/vtr_flow\/arch","journal-title":"Retrieved October 25, 2024 from https:\/\/github.com\/verilog-to-routing\/vtr-verilog-to-routing\/tree\/master\/vtr_flow\/arch"},{"key":"e_1_3_2_37_2","first-page":"1297","volume-title":"59th ACM\/IEEE Design Automation Conference","year":"2022","unstructured":"B. Wang, G. Shen, D. Li, J. Hao, W. Liu, Y. Huang, H. Wu, Y. Lin, G. Chen, and P. A. Heng. 2022. LHNN: Lattice hypergraph neural network for VLSI congestion prediction. In 59th ACM\/IEEE Design Automation Conference. 1297\u20131302."},{"key":"e_1_3_2_38_2","unstructured":"M. Wang D. Zheng Z. Ye Q. Gan M. Li X. Song J. Zhou C. Ma L. Yu Y. Gai T. Xiao T. He G. Karypis J. Li and Z. Zhang. 2019. Deep graph library: A graph-centric highly-performant package for graph neural networks. arXiv:1909.01315. Retrieved from https:\/\/arxiv.org\/abs\/1909.01315"},{"issue":"5","key":"e_1_3_2_39_2","first-page":"1","article-title":"WCPNet: Jointly predicting wirelength, congestion and power for FPGA using multi-task learning","volume":"29","year":"2024","unstructured":"J. Xian, Y. Xing, S. Cai, W. Li, X. Xiong, and Z. Hu. 2024. WCPNet: Jointly predicting wirelength, congestion and power for FPGA using multi-task learning. ACM Transactions on Design Automation of Electronic Systems 29, 5 (2024), 1\u201319.","journal-title":"ACM Transactions on Design Automation of Electronic Systems"},{"key":"e_1_3_2_40_2","first-page":"1","volume-title":"IEEE\/ACM International Conference on Computer-Aided Design","year":"2018","unstructured":"Z. Xie, Y.-H. Huang, G.-Q. Fang, H. Ren, S.-Y. Fang, and Y. Chen. 2018. RouteNet: Routability prediction for mixed-size designs using convolutional neural network. In IEEE\/ACM International Conference on Computer-Aided Design. 1\u20138."},{"key":"e_1_3_2_41_2","first-page":"1","volume-title":"56th Annual Design Automation Conference 2019","year":"2019","unstructured":"B. Xu, Y. Lin, X. Tang, S. Li, L. Shen, and N. Sun. 2019. Wellgan: Generative-adversarial-network-guided well generation for analog\/mixed-signal circuit layout. In 56th Annual Design Automation Conference 2019. 1\u20136."},{"key":"e_1_3_2_42_2","unstructured":"S. Yang Z. Yang D. Li Y. Zhang Z. Zhang G. Song and J. Hao. 2022. Versatile multi-stage graph neural network for circuit representation. In 36th International Conference on Neural Information Processing Systems 35 (2022) 20313\u201320324."},{"key":"e_1_3_2_43_2","first-page":"1","volume-title":"56th ACM\/IEEE Design Automation Conference","author":"Yu C.","year":"2019","unstructured":"C. Yu and Z. Zhang. 2019. Painting on placement: Forecasting routing congestion using conditional generative adversarial nets. In 56th ACM\/IEEE Design Automation Conference. 1\u20136."}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3773770","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,12,17]],"date-time":"2025-12-17T13:15:05Z","timestamp":1765977305000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3773770"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,12,17]]},"references-count":42,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2026,3,31]]}},"alternative-id":["10.1145\/3773770"],"URL":"https:\/\/doi.org\/10.1145\/3773770","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"value":"1084-4309","type":"print"},{"value":"1557-7309","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,12,17]]},"assertion":[{"value":"2025-03-11","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2025-10-18","order":2,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2025-12-17","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}