{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,4]],"date-time":"2026-07-04T11:15:51Z","timestamp":1783163751573,"version":"3.54.6"},"publisher-location":"New York, NY, USA","reference-count":14,"publisher":"ACM","license":[{"start":{"date-parts":[[2026,7,5]],"date-time":"2026-07-05T00:00:00Z","timestamp":1783209600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2026,7,6]]},"DOI":"10.1145\/3774895.3815549","type":"proceedings-article","created":{"date-parts":[[2026,6,30]],"date-time":"2026-06-30T09:18:16Z","timestamp":1782811096000},"page":"154-159","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["An Energy Characterization Study of ML operators in XNNPACK on RISC-V Vector Hardware"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0009-0003-4387-367X","authenticated-orcid":false,"given":"Ruimin","family":"Shi","sequence":"first","affiliation":[{"name":"KTH Royal Institute of Technology, Stockholm, Sweden"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0008-4601-069X","authenticated-orcid":false,"given":"Samuel","family":"Miksits","sequence":"additional","affiliation":[{"name":"KTH Royal Institute of Technology, Stockholm, Sweden"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0003-1777-562X","authenticated-orcid":false,"given":"Ron","family":"Minnich","sequence":"additional","affiliation":[{"name":"Hewlett Packard Enterprise, Livermore, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4229-5735","authenticated-orcid":false,"given":"Maya","family":"Gokhale","sequence":"additional","affiliation":[{"name":"Lawrence Livermore National Laboratory, Livermore, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4158-3583","authenticated-orcid":false,"given":"Ivy","family":"Peng","sequence":"additional","affiliation":[{"name":"KTH Royal Institute of Technology, Stockholm, Sweden"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2026,7,5]]},"reference":[{"key":"e_1_3_3_2_2_2","doi-asserted-by":"publisher","DOI":"10.1145\/3731599.3767531"},{"key":"e_1_3_3_2_3_2","unstructured":"Marat Dukhan. 2020. XNNPACK: Accelerated Neural Network Operations Library. https:\/\/github.com\/google\/XNNPACK."},{"key":"e_1_3_3_2_4_2","doi-asserted-by":"publisher","DOI":"10.1145\/3731599.3767535"},{"key":"e_1_3_3_2_5_2","unstructured":"Giulio Malenza Francesco Targa Adriano\u00a0Marques Garcia Marco Aldinucci and Robert Birke. 2025. Exploring energy consumption of AI frameworks on a 64-core RV64 Server CPU. arxiv:https:\/\/arXiv.org\/abs\/2504.03774\u00a0[cs.DC] https:\/\/arxiv.org\/abs\/2504.03774"},{"key":"e_1_3_3_2_6_2","doi-asserted-by":"publisher","unstructured":"Adriano Marques Garcia Giulio Malenza Robert Birke and Marco Aldinucci. 2026. Inference performance of large language models on a 64-core RISC-V CPU with silicon-enabled vectors. Future Generation Computer Systems 177 (2026) 108242. 10.1016\/j.future.2025.108242","DOI":"10.1016\/j.future.2025.108242"},{"key":"e_1_3_3_2_7_2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-031-97632-2_11"},{"key":"e_1_3_3_2_8_2","doi-asserted-by":"crossref","unstructured":"Matteo Perotti Matheus Cavalcante Renzo Andri Lukas Cavigelli and Luca Benini. 2024. Ara2: Exploring single-and multi-core vector processing with an efficient RVV 1.0 compliant open-source processor. IEEE Trans. Comput. 73 7 (2024) 1822\u20131836.","DOI":"10.1109\/TC.2024.3388896"},{"key":"e_1_3_3_2_9_2","unstructured":"Banana Pi. 2024. BPI-F3 SpacemiT K1chip BPI-F3 DEB1 scenario power consumption data. https:\/\/forum.banana-pi.org\/t\/bpi-f3-spacemit-k1chip-bpi-f3-deb1-scenario-power-consumption-data\/18464"},{"key":"e_1_3_3_2_10_2","volume-title":"The RISC-V Vector Extension, Version 1.0","author":"International RISC-V","year":"2021","unstructured":"RISC-V International. 2021. The RISC-V Vector Extension, Version 1.0. Technical Report. RISC-V International. https:\/\/github.com\/riscv\/riscv-v-spec"},{"key":"e_1_3_3_2_11_2","unstructured":"Ruimin Shi Maya Gokhale Pei-Hung Lin Xavier Teruel and Ivy Peng. 2026. Closer in the Gap: Towards Portable Performance on RISC-V Vector Processors. arxiv:https:\/\/arXiv.org\/abs\/2605.10860\u00a0[cs.DC] https:\/\/arxiv.org\/abs\/2605.10860"},{"key":"e_1_3_3_2_12_2","first-page":"33","volume-title":"European Conference on Parallel Processing","author":"Shi Ruimin","year":"2025","unstructured":"Ruimin Shi, Gabin Schieffer, Maya Gokhale, Pei-Hung Lin, Hiren Patel, and Ivy Peng. 2025. ARM SVE Unleashed: Performance and Insights Across HPC Applications on Nvidia Grace. In European Conference on Parallel Processing. Springer, Springer Nature Switzerland, Cham, 33\u201347."},{"key":"e_1_3_3_2_13_2","unstructured":"Ruimin Shi Gabin Schieffer Pei-Hung Lin Maya Gokhale Andreas Herten and Ivy Peng. 2026. High-performance Vector-length Agnostic Quantum Circuit Simulations on ARM Processors. arxiv:https:\/\/arXiv.org\/abs\/2602.09604\u00a0[cs.DC] https:\/\/arxiv.org\/abs\/2602.09604"},{"key":"e_1_3_3_2_14_2","volume-title":"SiFive Accelerates RISC-V Vector Integration in XNNPACK for Optimized AI Inference","year":"2024","unstructured":"SiFive. 2024. SiFive Accelerates RISC-V Vector Integration in XNNPACK for Optimized AI Inference. https:\/\/www.sifive.com\/blog\/sifive-accelerates-risc-v-vector-integration-in-xnnpack-for-optimized-ai-inference Accessed: 2026-04-20."},{"key":"e_1_3_3_2_15_2","doi-asserted-by":"publisher","DOI":"10.1145\/3679240.3735101"}],"event":{"name":"ICS Workshops '26: 2026 International Conference on Supercomputing Workshops","location":"Belfast , Northern Ireland , United Kingdom","acronym":"ICS Workshops '26"},"container-title":["Proceedings of the 40th ACM International Conference on Supercomputing - Workshops"],"original-title":[],"deposited":{"date-parts":[[2026,7,4]],"date-time":"2026-07-04T10:21:34Z","timestamp":1783160494000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3774895.3815549"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,7,5]]},"references-count":14,"alternative-id":["10.1145\/3774895.3815549","10.1145\/3774895"],"URL":"https:\/\/doi.org\/10.1145\/3774895.3815549","relation":{},"subject":[],"published":{"date-parts":[[2026,7,5]]},"assertion":[{"value":"2026-07-05","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}