{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,4]],"date-time":"2026-07-04T11:16:04Z","timestamp":1783163764009,"version":"3.54.6"},"publisher-location":"New York, NY, USA","reference-count":104,"publisher":"ACM","license":[{"start":{"date-parts":[[2026,7,5]],"date-time":"2026-07-05T00:00:00Z","timestamp":1783209600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2026,7,6]]},"DOI":"10.1145\/3774895.3819989","type":"proceedings-article","created":{"date-parts":[[2026,6,30]],"date-time":"2026-06-30T09:18:16Z","timestamp":1782811096000},"page":"6-11","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["Memory-Centric Computing: Security Benefits and Challenges of Processing-in-DRAM"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-3310-4423","authenticated-orcid":false,"given":"Ismail Emir","family":"Yuksel","sequence":"first","affiliation":[{"name":"ETH Zurich, SAFARI Research Group, Zurich, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2718-0297","authenticated-orcid":false,"given":"Fatma Nisa","family":"Bostanci","sequence":"additional","affiliation":[{"name":"ETH Zurich, SAFARI Research Group, Zurich, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5333-5726","authenticated-orcid":false,"given":"Ataberk","family":"Olgun","sequence":"additional","affiliation":[{"name":"ETH Zurich, SAFARI Research Group, Zurich, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0075-2312","authenticated-orcid":false,"given":"Onur","family":"Mutlu","sequence":"additional","affiliation":[{"name":"ETH Zurich, SAFARI Research Group, Zurich, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2026,7,5]]},"reference":[{"key":"e_1_3_3_1_2_2","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750385"},{"key":"e_1_3_3_1_3_2","unstructured":"Junwhan Ahn et\u00a0al. 2023. Retrospective: A Scalable Processing-in-memory Accelerator for Parallel Graph Processing. arXiv."},{"key":"e_1_3_3_1_4_2","doi-asserted-by":"crossref","unstructured":"Mohammed Alser et\u00a0al. 2022. From Molecules to Genomic Variations: Accelerating Genome Analysis via Intelligent Algorithms and Architectures. CSBJ (2022).","DOI":"10.1016\/j.csbj.2022.08.019"},{"key":"e_1_3_3_1_5_2","doi-asserted-by":"crossref","unstructured":"Nikolaos\u00a0Athanasios Anagnostopoulos et\u00a0al. 2018. Intrinsic Run-Time Row Hammer PUFs: Leveraging the Row Hammer Effect for Run-Time Cryptography and Improved Security. Cryptography (2018).","DOI":"10.20944\/preprints201804.0369.v1"},{"key":"e_1_3_3_1_6_2","doi-asserted-by":"crossref","unstructured":"B.\u00a0M.\u00a0S. Bahar\u00a0Talukder et\u00a0al. 2019. PreLatPUF: Exploiting DRAM Latency Variations for Generating Robust Device Signatures. IEEE Access (2019).","DOI":"10.1109\/ICCE.2019.8662060"},{"key":"e_1_3_3_1_7_2","unstructured":"Umut Baser et\u00a0al. 2026. In-DRAM Signature Generation Using Simultaneous Multiple-Row Activation: An Experimental Study of Off-The-Shelf DRAM Chips. arXiv."},{"key":"e_1_3_3_1_8_2","doi-asserted-by":"crossref","unstructured":"Lawrence Bassham et\u00a0al. 2010. A Statistical Test Suite for Random and Pseudorandom Number Generators for Cryptographic Applications. Special Publication (NIST SP).","DOI":"10.6028\/NIST.SP.800-22r1a"},{"key":"e_1_3_3_1_9_2","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2015.7140228"},{"key":"e_1_3_3_1_10_2","doi-asserted-by":"publisher","DOI":"10.1145\/3173162.3173177"},{"key":"e_1_3_3_1_11_2","doi-asserted-by":"publisher","DOI":"10.1109\/PACT52795.2021.00019"},{"key":"e_1_3_3_1_12_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA53966.2022.00087"},{"key":"e_1_3_3_1_13_2","doi-asserted-by":"publisher","DOI":"10.1109\/DSN64029.2025.00018"},{"key":"e_1_3_3_1_14_2","doi-asserted-by":"crossref","unstructured":"F.\u00a0Nisa Bostanc\u0131 et\u00a0al. 2026. Extended Abstract: Re-Evaluating the Real-System Modeling Accuracy of Ramulator 2.0. The 3rd Tutorial on Ramulator and DRAM Bender colocated with ICS.","DOI":"10.1145\/3774895.3820146"},{"key":"e_1_3_3_1_15_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2006.1696222"},{"key":"e_1_3_3_1_16_2","doi-asserted-by":"crossref","unstructured":"M. Bucci et\u00a0al. 2003. A High-speed Oscillator-based Truly Random Number Source for Cryptographic Applications on a Smart Card IC. TC (2003).","DOI":"10.1109\/TC.2003.1190581"},{"key":"e_1_3_3_1_17_2","doi-asserted-by":"crossref","unstructured":"Y. Cai et\u00a0al. 2017. Error Characterization Mitigation and Recovery in Flash Memory Based Solid-State Drives. Proc. IEEE (2017).","DOI":"10.1109\/JPROC.2017.2713127"},{"key":"e_1_3_3_1_18_2","unstructured":"Yu Cai et\u00a0al. 2017. Errors in Flash-Memory-Based Solid-State Drives: Analysis Mitigation and Recovery. arXiv preprint arXiv:https:\/\/arXiv.org\/abs\/1711.11427 (2017)."},{"key":"e_1_3_3_1_19_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCC.2011.30"},{"key":"e_1_3_3_1_20_2","volume-title":"MAPLD","author":"Chu P.\u00a0P.","year":"1999","unstructured":"P.\u00a0P. Chu et\u00a0al. 1999. Design Techniques of FPGA Based Random Number Generator. In MAPLD."},{"key":"e_1_3_3_1_21_2","doi-asserted-by":"crossref","unstructured":"Geraldo\u00a0F. de Oliveira et\u00a0al. 2021. DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks. IEEE Access (2021).","DOI":"10.1109\/ACCESS.2021.3110993"},{"key":"e_1_3_3_1_22_2","unstructured":"Robert\u00a0H. Dennard. 1968. Field-Effect Transistor Memory."},{"key":"e_1_3_3_1_23_2","volume-title":"CCS","author":"Dorrendorf L.","year":"2007","unstructured":"L. Dorrendorf et\u00a0al. 2007. Cryptanalysis of the Windows Random Number Generator. In CCS."},{"key":"e_1_3_3_1_24_2","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2017.8053159"},{"key":"e_1_3_3_1_25_2","unstructured":"FIPS PUB. 2012. 180-2: Secure hash standard (SHS). US Department of Commerce National Institute of Standards and Technology (NIST) (2012)."},{"key":"e_1_3_3_1_26_2","volume-title":"ISM","author":"Fischer Bernhard","year":"2024","unstructured":"Bernhard Fischer et\u00a0al. 2024. Leveraging Rowhammer for Physically Unique and Non-tamperable Device Identification. In ISM."},{"key":"e_1_3_3_1_27_2","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358260"},{"key":"e_1_3_3_1_28_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO56248.2022.00066"},{"key":"e_1_3_3_1_29_2","volume-title":"CCS","author":"Gassend Blaise","year":"2002","unstructured":"Blaise Gassend et\u00a0al. 2002. Silicon Physical Random Functions. In CCS."},{"key":"e_1_3_3_1_30_2","volume-title":"ISCA","author":"Ghiasi Nika\u00a0Mansouri","year":"2024","unstructured":"Nika\u00a0Mansouri Ghiasi et\u00a0al. 2024. MegIS: High-Performance, Energy-Efficient, and Low-Cost Metagenomic Analysis with In-Storage Processing. In ISCA."},{"key":"e_1_3_3_1_31_2","unstructured":"Saugata Ghose et\u00a0al. 2019. Processing-in-Memory: A Workload-Driven Perspective. IBM JRD (2019)."},{"key":"e_1_3_3_1_32_2","doi-asserted-by":"crossref","unstructured":"Juan G\u00f3mez-Luna et\u00a0al. 2022. Benchmarking a New Paradigm: Experimental Analysis and Characterization of a Real Processing-in-Memory System. IEEE Access (2022).","DOI":"10.1109\/ACCESS.2022.3174101"},{"key":"e_1_3_3_1_33_2","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2006.5"},{"key":"e_1_3_3_1_34_2","volume-title":"DATE","author":"Hashemian Maryam\u00a0S.","year":"2015","unstructured":"Maryam\u00a0S. Hashemian et\u00a0al. 2015. A Robust Authentication Methodology Using Physically Unclonable Functions in DRAM Arrays. In DATE."},{"key":"e_1_3_3_1_35_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.62"},{"key":"e_1_3_3_1_36_2","unstructured":"Yintao He et\u00a0al. 2025. PAPI: Exploiting Dynamic Parallelism in Large Language Model Decoding with a Processing-In-Memory-Enabled Computing System. ASPLOS (2025)."},{"key":"e_1_3_3_1_37_2","doi-asserted-by":"publisher","DOI":"10.1145\/3620666.3651380"},{"key":"e_1_3_3_1_38_2","volume-title":"RFID","author":"Holcomb D.\u00a0E.","year":"2007","unstructured":"D.\u00a0E. Holcomb et\u00a0al. 2007. Initial SRAM State as a Fingerprint and Source of True Random Numbers for RFID Tags. In RFID."},{"key":"e_1_3_3_1_39_2","doi-asserted-by":"crossref","unstructured":"D.\u00a0E. Holcomb et\u00a0al. 2009. Power-Up SRAM State as an Identifying Fingerprint and Source of True Random Numbers. TC (2009).","DOI":"10.1109\/TC.2008.212"},{"key":"e_1_3_3_1_40_2","doi-asserted-by":"crossref","unstructured":"J. Holleman et\u00a0al. 2008. A 3mu W CMOS True Random Number Generator with Adaptive Floating-Gate Offset Cancellation. JSSC (2008).","DOI":"10.1109\/JSSC.2008.920327"},{"key":"e_1_3_3_1_41_2","volume-title":"JESD79-5c: DDR5 SDRAM Standard","year":"2024","unstructured":"JEDEC. 2024. JESD79-5c: DDR5 SDRAM Standard."},{"key":"e_1_3_3_1_42_2","volume-title":"ISCA","author":"Kakolyris Andreas\u00a0Kosmas","year":"2026","unstructured":"Andreas\u00a0Kosmas Kakolyris et\u00a0al. 2026. ColumnKeeper: Efficient Solutions for Mitigating ColumnDisturb in DRAM-based Systems. In ISCA."},{"key":"e_1_3_3_1_43_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2014.6865740"},{"key":"e_1_3_3_1_44_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2018.00026"},{"key":"e_1_3_3_1_45_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2019.00011"},{"key":"e_1_3_3_1_46_2","volume-title":"ISCA","author":"Kim Y.","year":"2014","unstructured":"Y. Kim et\u00a0al. 2014. Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors. In ISCA."},{"key":"e_1_3_3_1_47_2","volume-title":"ESSCIRC","author":"Kinniment D.","year":"2002","unstructured":"D. Kinniment et\u00a0al. 2002. Design of an On-chip Random Number Generator using Metastability. In ESSCIRC."},{"key":"e_1_3_3_1_48_2","volume-title":"SENSORS","author":"Kumari Indra","year":"2018","unstructured":"Indra Kumari et\u00a0al. 2018. Rapid Run-Time DRAM PUF Based on Bit-Flip Position for Secure IoT Devices. In SENSORS."},{"key":"e_1_3_3_1_49_2","doi-asserted-by":"publisher","DOI":"10.1109\/TrustCom60117.2023.00144"},{"key":"e_1_3_3_1_50_2","doi-asserted-by":"publisher","DOI":"10.1109\/IS3C.2014.188"},{"key":"e_1_3_3_1_51_2","volume-title":"ISCA","author":"Luo Haocong","year":"2023","unstructured":"Haocong Luo et\u00a0al. 2023. RowPress: Amplifying Read Disturbance in Modern DRAM Chips. In ISCA."},{"key":"e_1_3_3_1_52_2","unstructured":"Haocong Luo et\u00a0al. 2026. Ramulator 2.1: A Composable Memory System Simulator for Modern DRAM Systems. The 3rd Tutorial on Ramulator and DRAM Bender colocated with ICS."},{"key":"e_1_3_3_1_53_2","unstructured":"Jos\u00e9\u00a0F. Mart\u00ednez et\u00a0al. 2023. Retrospective: Self-optimizing Memory Controllers: A Reinforcement Learning Approach. Retrospective Issue for ISCA-50."},{"key":"e_1_3_3_1_54_2","doi-asserted-by":"crossref","unstructured":"Nico Mexis et\u00a0al. 2025. Achieving Error-Free Lightweight Authentication With DRAM-Based Physical Unclonable Functions. TCAS-I (2025).","DOI":"10.1109\/TCSI.2024.3480852"},{"key":"e_1_3_3_1_55_2","doi-asserted-by":"crossref","unstructured":"Jack Miskelly et\u00a0al. 2020. Fast DRAM PUFs on Commodity Devices. TCAD (2020).","DOI":"10.1109\/TCAD.2020.3012218"},{"key":"e_1_3_3_1_56_2","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2013.6582088"},{"key":"e_1_3_3_1_57_2","volume-title":"DATE","author":"Mutlu Onur","year":"2017","unstructured":"Onur Mutlu. 2017. The RowHammer Problem and Other Issues We May Face as Memory Becomes Denser. In DATE."},{"key":"e_1_3_3_1_58_2","volume-title":"DATE","author":"Mutlu Onur","year":"2020","unstructured":"Onur Mutlu. 2020. Intelligent Architectures for Intelligent Computing Systems. In DATE."},{"key":"e_1_3_3_1_59_2","unstructured":"Onur Mutlu. 2023. Retrospective: An Experimental Study of Data Retention Behavior in Modern DRAM Devices: Implications for Retention Time Profiling Mechanisms. Retrospective Issue for ISCA-50."},{"key":"e_1_3_3_1_60_2","unstructured":"Onur Mutlu. 2023. Retrospective: Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors. Retrospective Issue for ISCA-50."},{"key":"e_1_3_3_1_61_2","unstructured":"Onur Mutlu. 2023. Retrospective: RAIDR: Retention-Aware Intelligent DRAM Refresh. Retrospective Issue for ISCA-50."},{"key":"e_1_3_3_1_62_2","unstructured":"Onur Mutlu et\u00a0al. 2014. Research Problems and Opportunities in Memory Systems. SUPERFRI (2014)."},{"key":"e_1_3_3_1_63_2","unstructured":"Onur Mutlu et\u00a0al. 2015. The Main Memory System: Challenges and Opportunities. Communications of the KIISE (2015)."},{"key":"e_1_3_3_1_64_2","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3323476"},{"key":"e_1_3_3_1_65_2","doi-asserted-by":"crossref","unstructured":"Onur Mutlu et\u00a0al. 2019. Processing Data Where It Makes Sense: Enabling In-Memory Computation. MICPRO (2019).","DOI":"10.1145\/3299874.3322805"},{"key":"e_1_3_3_1_66_2","unstructured":"Onur Mutlu et\u00a0al. 2019. RowHammer: A Retrospective. TCAD (2019)."},{"key":"e_1_3_3_1_67_2","doi-asserted-by":"publisher","DOI":"10.1145\/3566097.3568350"},{"key":"e_1_3_3_1_68_2","volume-title":"IEDM","author":"Mutlu Onur","year":"2024","unstructured":"Onur Mutlu et\u00a0al. 2024. Memory-Centric Computing: Recent Advances in Processing-in-DRAM. In IEDM."},{"key":"e_1_3_3_1_69_2","unstructured":"Onur Mutlu et\u00a0al. 2025. A Modern Primer on Processing in Memory. arXiv."},{"key":"e_1_3_3_1_70_2","doi-asserted-by":"publisher","DOI":"10.1109\/IMW61990.2025.11026935"},{"key":"e_1_3_3_1_71_2","doi-asserted-by":"crossref","unstructured":"Fatemeh Najafi et\u00a0al. 2021. Deep PUF: A Highly Reliable DRAM PUF-Based Authentication for IoT Networks Using Deep Convolutional Neural Networks. Sensors (2021).","DOI":"10.3390\/s21062009"},{"key":"e_1_3_3_1_72_2","doi-asserted-by":"crossref","unstructured":"Fatemeh Najafi et\u00a0al. 2025. EPUF: An Entropy-Derived Latency-Based DRAM Physical Unclonable Function for Lightweight Authentication in Internet of Things. TMC (2025).","DOI":"10.1109\/TMC.2024.3494612"},{"key":"e_1_3_3_1_73_2","volume-title":"ISCA","author":"Olgun Ataberk","year":"2021","unstructured":"Ataberk Olgun et\u00a0al. 2021. QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips. In ISCA."},{"key":"e_1_3_3_1_74_2","doi-asserted-by":"crossref","unstructured":"Ataberk Olgun et\u00a0al. 2022. PiDRAM: A Holistic End-to-end FPGA-based Framework for Processing-in-DRAM. TACO (2022).","DOI":"10.1145\/3563697"},{"key":"e_1_3_3_1_75_2","doi-asserted-by":"crossref","unstructured":"Ataberk Olgun et\u00a0al. 2023. DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chips. TCAD (2023).","DOI":"10.1109\/TCAD.2023.3282172"},{"key":"e_1_3_3_1_76_2","unstructured":"Ataberk Olgun et\u00a0al. 2026. A Modern Large-Scale Memory Characterization Laboratory. The 3rd Tutorial on Ramulator and DRAM Bender colocated with ICS."},{"key":"e_1_3_3_1_77_2","doi-asserted-by":"crossref","unstructured":"Geraldo\u00a0F Oliveira et\u00a0al. 2022. Accelerating Neural Network Inference with Processing-in-DRAM: From the Edge to the Cloud. IEEE Micro (2022).","DOI":"10.1109\/MM.2022.3202350"},{"key":"e_1_3_3_1_78_2","volume-title":"ISCA","author":"Orosa Lois","year":"2021","unstructured":"Lois Orosa et\u00a0al. 2021. CODIC: A Low-Cost Substrate for Enabling Custom In-DRAM Functionalities and Optimizations. In ISCA."},{"key":"e_1_3_3_1_79_2","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIR.2006.307548"},{"key":"e_1_3_3_1_80_2","doi-asserted-by":"publisher","DOI":"10.1145\/3620665.3640422"},{"key":"e_1_3_3_1_81_2","doi-asserted-by":"publisher","DOI":"10.1049\/el:20091899"},{"key":"e_1_3_3_1_82_2","doi-asserted-by":"crossref","unstructured":"B. Ray et\u00a0al. 2018. True Random Number Generation Using Read Noise of Flash Memory Cells. IEEE Trans. on Electron Devices (2018).","DOI":"10.1109\/TED.2018.2792436"},{"key":"e_1_3_3_1_83_2","unstructured":"SAFARI Research Group. 2017. SoftMC \u2014 GitHub Repository. https:\/\/github.com\/CMU-SAFARI\/softmc."},{"key":"e_1_3_3_1_84_2","unstructured":"SAFARI Research Group. 2022. DRAM Bender \u2014 GitHub Repository. https:\/\/github.com\/CMU-SAFARI\/DRAM-Bender."},{"key":"e_1_3_3_1_85_2","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2017.7951729"},{"key":"e_1_3_3_1_86_2","doi-asserted-by":"crossref","unstructured":"Andr\u00e9 Schaller et\u00a0al. 2019. Decay-Based DRAM PUFs in Commodity Devices. TDSC (2019).","DOI":"10.1109\/TDSC.2018.2822298"},{"key":"e_1_3_3_1_87_2","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540725"},{"key":"e_1_3_3_1_88_2","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3124544"},{"key":"e_1_3_3_1_89_2","doi-asserted-by":"crossref","unstructured":"Gagandeep Singh et\u00a0al. 2021. FPGA-Based Near-Memory Acceleration of Modern Data-Intensive Applications. IEEE Micro (2021).","DOI":"10.1109\/MM.2021.3088396"},{"key":"e_1_3_3_1_90_2","doi-asserted-by":"publisher","DOI":"10.1145\/3105915"},{"key":"e_1_3_3_1_91_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCE.2019.8662060"},{"key":"e_1_3_3_1_92_2","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2016.7495561"},{"key":"e_1_3_3_1_93_2","doi-asserted-by":"crossref","unstructured":"C. Tokunaga et\u00a0al. 2008. True Random Number Generator with a Metastability-based Quality Control. JSSC (2008).","DOI":"10.1109\/JSSC.2007.910965"},{"key":"e_1_3_3_1_94_2","doi-asserted-by":"publisher","DOI":"10.1145\/1342250.1342263"},{"key":"e_1_3_3_1_95_2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-28368-0_20"},{"key":"e_1_3_3_1_96_2","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2012.12"},{"key":"e_1_3_3_1_97_2","unstructured":"P.\u00a0Z. Wieczorek. [n. d.]. An FPGA Implementation of the Resolve Time-based True Random Number Generator with Quality Control."},{"key":"e_1_3_3_1_98_2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-662-53140-2_21"},{"key":"e_1_3_3_1_99_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2015.7372560"},{"key":"e_1_3_3_1_100_2","doi-asserted-by":"crossref","unstructured":"K. Yang et\u00a0al. 2016. An All-digital Edge Racing True Random Number Generator Robust Against PVT Variations. JSSC (2016).","DOI":"10.1109\/JSSC.2016.2519383"},{"key":"e_1_3_3_1_101_2","doi-asserted-by":"publisher","DOI":"10.1109\/DSN58291.2024.00024"},{"key":"e_1_3_3_1_102_2","doi-asserted-by":"publisher","DOI":"10.1145\/3725843.3756022"},{"key":"e_1_3_3_1_103_2","volume-title":"ICCD","author":"Yuksel Ismail\u00a0Emir","year":"2025","unstructured":"Ismail\u00a0Emir Yuksel et\u00a0al. 2025. In-DRAM True Random Number Generation Using Simultaneous Multiple-Row Activation: An Experimental Study of Real DRAM Chips. In ICCD."},{"key":"e_1_3_3_1_104_2","volume-title":"ISCA","author":"Yuksel Ismail\u00a0Emir","year":"2025","unstructured":"Ismail\u00a0Emir Yuksel et\u00a0al. 2025. PuDHammer: Experimental Analysis of Read Disturbance Effects of Processing-using-DRAM in Real DRAM Chips. In ISCA."},{"key":"e_1_3_3_1_105_2","volume-title":"NaNA","author":"Zheng Yu","year":"2021","unstructured":"Yu Zheng et\u00a0al. 2021. Implementation and Analysis of Hybrid DRAM PUFs on FPGA. In NaNA."}],"event":{"name":"ICS Workshops '26: 2026 International Conference on Supercomputing Workshops","location":"Belfast , Northern Ireland , United Kingdom","acronym":"ICS Workshops '26"},"container-title":["Proceedings of the 40th ACM International Conference on Supercomputing - Workshops"],"original-title":[],"deposited":{"date-parts":[[2026,7,4]],"date-time":"2026-07-04T10:22:25Z","timestamp":1783160545000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3774895.3819989"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,7,5]]},"references-count":104,"alternative-id":["10.1145\/3774895.3819989","10.1145\/3774895"],"URL":"https:\/\/doi.org\/10.1145\/3774895.3819989","relation":{},"subject":[],"published":{"date-parts":[[2026,7,5]]},"assertion":[{"value":"2026-07-05","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}