{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,4]],"date-time":"2026-07-04T11:16:05Z","timestamp":1783163765355,"version":"3.54.6"},"publisher-location":"New York, NY, USA","reference-count":208,"publisher":"ACM","license":[{"start":{"date-parts":[[2026,7,5]],"date-time":"2026-07-05T00:00:00Z","timestamp":1783209600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2026,7,6]]},"DOI":"10.1145\/3774895.3820147","type":"proceedings-article","created":{"date-parts":[[2026,6,30]],"date-time":"2026-06-30T09:18:16Z","timestamp":1782811096000},"page":"164-172","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["A Modern Large-Scale Memory Characterization Laboratory"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-5333-5726","authenticated-orcid":false,"given":"Ataberk","family":"Olgun","sequence":"first","affiliation":[{"name":"ETH Zurich, Zurich, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0009-0849-8724","authenticated-orcid":false,"given":"Haocong","family":"Luo","sequence":"additional","affiliation":[{"name":"ETH Zurich, Zurich, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3310-4423","authenticated-orcid":false,"given":"Ismail Emir","family":"Yuksel","sequence":"additional","affiliation":[{"name":"ETH Zurich, Zurich, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2718-0297","authenticated-orcid":false,"given":"Fatma Nisa","family":"Bostanci","sequence":"additional","affiliation":[{"name":"ETH Zurich, Zurich, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9333-6077","authenticated-orcid":false,"given":"Abdullah Giray","family":"Yaglikci","sequence":"additional","affiliation":[{"name":"ETH Zurich, Zurich, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0075-2312","authenticated-orcid":false,"given":"Onur","family":"Mutlu","sequence":"additional","affiliation":[{"name":"ETH Zurich, SAFARI Research Group, Zurich, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2026,7,5]]},"reference":[{"key":"e_1_3_3_2_2_2","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750386"},{"key":"e_1_3_3_2_3_2","unstructured":"Junwhan Ahn Sungpack Hong Sungjoo Yoo Onur Mutlu and Kiyoung Choi. 2023. Retrospective: A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing. Retrospective Issue for ISCA-50."},{"key":"e_1_3_3_2_4_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO56248.2022.00085"},{"key":"e_1_3_3_2_5_2","unstructured":"AMD. 2026. Alveo Data Center Accelerator Card Management System User Guide (UG1468). https:\/\/docs.amd.com\/r\/en-US\/pg348-cms-subsystem."},{"key":"e_1_3_3_2_6_2","unstructured":"AMD. 2026. Alveo U55C FPGA Board. https:\/\/www.amd.com\/en\/products\/accelerators\/alveo\/u55c\/a-u55c-p00g-pq-g.html."},{"key":"e_1_3_3_2_7_2","unstructured":"AMD. 2026. AMD Alveo U50 FPGA Board. https:\/\/www.amd.com\/en\/products\/accelerators\/alveo\/u50\/a-u50-p00g-pq-g.html."},{"key":"e_1_3_3_2_8_2","unstructured":"Apple Inc.2015. About the Security Content of Mac EFI Security Update 2015-001. https:\/\/support.apple.com\/en-us\/HT204934."},{"key":"e_1_3_3_2_9_2","doi-asserted-by":"crossref","unstructured":"Kerem Ar\u0131kan Alessandro Palumbo Luca Cassano Pedro Reviriego Salvatore Pontarelli Giuseppe Bianchi O\u011fuz Ergin and Marco Ottavi. 2022. Processor Security: Detecting Microarchitectural Attacks via Count-Min Sketches. VLSI (2022).","DOI":"10.1109\/TVLSI.2022.3171810"},{"key":"e_1_3_3_2_10_2","doi-asserted-by":"publisher","DOI":"10.1145\/2872362.2872390"},{"key":"e_1_3_3_2_11_2","doi-asserted-by":"publisher","DOI":"10.1145\/3669940.3707242"},{"key":"e_1_3_3_2_12_2","unstructured":"K.S. Bains et\u00a0al. 2015. Method Apparatus and System for Providing a Memory Refresh. U.S. Patent: 9 030 903."},{"key":"e_1_3_3_2_13_2","unstructured":"K. Bains et\u00a0al. 2015. Row Hammer Refresh Command. U.S. Patents: 9 117 544 9 236 110 10 210 925."},{"key":"e_1_3_3_2_14_2","unstructured":"Kuljit\u00a0S Bains and John\u00a0B Halbert. 2016. Distributed Row Hammer Tracking. U.S. Patent: 9 299 400."},{"key":"e_1_3_3_2_15_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2009.4919648"},{"key":"e_1_3_3_2_16_2","volume-title":"DSN Disrupt","author":"Baser Umut","year":"2026","unstructured":"Umut Baser, Ismail\u00a0Emir Yuksel, F.\u00a0Nisa Bostanci, Konstantinos Sgouras, Ataberk Olgun, Emre\u00a0H. Demirli, Zhiheng Yue, Harsh Songara, O\u011fuz Ergin, and Onur Mutlu. 2026. In-DRAM Signature Generation Using Simultaneous Multiple-Row Activation: An Experimental Study of Off-The-Shelf DRAM Chips. In DSN Disrupt."},{"key":"e_1_3_3_2_17_2","volume-title":"DRAMSec","author":"Bennett Tanj","year":"2021","unstructured":"Tanj Bennett, Stefan Saroiu, Alec Wolman, and Lucian Cojocar. 2021. Panopticon: A Complete In-DRAM Rowhammer Mitigation. In DRAMSec."},{"key":"e_1_3_3_2_18_2","doi-asserted-by":"crossref","unstructured":"Md\u00a0Kawser Bepary Bashir Mohammad Sabquat\u00a0Bahar Talukder and Md\u00a0Tauhidur Rahman. 2022. DRAM Retention Behavior with Accelerated Aging in Commercial Chips. Applied Sciences (2022).","DOI":"10.3390\/app12094332"},{"key":"e_1_3_3_2_19_2","unstructured":"Bittware. [n. d.]. Bittware XUPVVH FPGA Board. https:\/\/www.bittware.com\/fpga\/xup-vvh\/."},{"key":"e_1_3_3_2_20_2","doi-asserted-by":"publisher","DOI":"10.1109\/PACT52795.2021.00019"},{"key":"e_1_3_3_2_21_2","doi-asserted-by":"publisher","DOI":"10.1145\/3173162.3173177"},{"key":"e_1_3_3_2_22_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS69572.2026.00029"},{"key":"e_1_3_3_2_23_2","doi-asserted-by":"crossref","unstructured":"F.\u00a0Nisa Bostanci Haocong Luo Ataberk Olgun Maria Makeenkova Geraldo F.\u00a0De Oliveira A.\u00a0Giray Yaglikci and Onur Mutlu. 2026. Extended Abstract: Re-Evaluating the Real-System Modeling Accuracy of Ramulator 2.0. The 3rd Tutorial on Ramulator and DRAM Bender colocated with ICS.","DOI":"10.1145\/3774895.3820146"},{"key":"e_1_3_3_2_24_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA57654.2024.00050"},{"key":"e_1_3_3_2_25_2","volume-title":"USENIX Security","author":"Brasser Ferdinand","year":"2017","unstructured":"Ferdinand Brasser, Lucas Davi, David Gens, Christopher Liebchen, and Ahmad-Reza Sadeghi. 2017. Can\u2019t Touch This: Software-Only Mitigation Against Rowhammer Attacks Targeting Kernel Memory. In USENIX Security."},{"key":"e_1_3_3_2_26_2","volume-title":"NIPS","author":"Brown Tom\u00a0B.","year":"2020","unstructured":"Tom\u00a0B. Brown, Benjamin Mann, Nick Ryder, Melanie Subbiah, Jared Kaplan, Prafulla Dhariwal, Arvind Neelakantan, Pranav Shyam, Girish Sastry, Amanda Askell, Sandhini Agarwal, Ariel Herbert-Voss, Gretchen Krueger, Tom Henighan, Rewon Child, Aditya Ramesh, Daniel\u00a0M. Ziegler, Jeffrey Wu, Clemens Winter, Christopher Hesse, Mark Chen, Eric Sigler, Mateusz Litwin, Scott Gray, Benjamin Chess, Jack Clark, Christopher Berner, Sam McCandlish, Alec Radford, Ilya Sutskever, and Dario Amodei. 2020. Language Models are Few-Shot Learners. In NIPS."},{"key":"e_1_3_3_2_27_2","doi-asserted-by":"crossref","unstructured":"Y. Cai S. Ghose E.\u00a0F. Haratsch Y. Luo and O. Mutlu. 2017. Error Characterization Mitigation and Recovery in Flash Memory Based Solid-State Drives. Proc. IEEE (2017).","DOI":"10.1109\/JPROC.2017.2713127"},{"key":"e_1_3_3_2_28_2","unstructured":"Yu Cai Saugata Ghose Erich\u00a0F Haratsch Yixin Luo and Onur Mutlu. 2017. Errors in Flash-Memory-Based Solid-State Drives: Analysis Mitigation and Recovery. arXiv preprint arXiv:https:\/\/arXiv.org\/abs\/1711.11427 (2017)."},{"key":"e_1_3_3_2_29_2","doi-asserted-by":"publisher","DOI":"10.1109\/DSN64029.2025.00042"},{"key":"e_1_3_3_2_30_2","volume-title":"DRAMSec","author":"Canpolat Oguzhan","year":"2024","unstructured":"Oguzhan Canpolat, Abdullah\u00a0Giray Yaglikci, Geraldo\u00a0F. Oliveira, Ataberk Olgun, Oguz Ergin, and Onur Mutlu. 2024. Understanding the Security Benefits and Overheads of Emerging Industry Solutions to DRAM Read Disturbance. In DRAMSec."},{"key":"e_1_3_3_2_31_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA61900.2025.00071"},{"key":"e_1_3_3_2_32_2","doi-asserted-by":"publisher","DOI":"10.1145\/2896377.2901453"},{"key":"e_1_3_3_2_33_2","doi-asserted-by":"publisher","DOI":"10.1145\/3078505.3078590"},{"key":"e_1_3_3_2_34_2","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306797"},{"key":"e_1_3_3_2_35_2","unstructured":"Robert\u00a0H. Dennard. 1968. Field-Effect Transistor Memory. U.S. Patent 3 387 286."},{"key":"e_1_3_3_2_36_2","unstructured":"Fabrice Devaux and Renaud Ayrignac. 2021. Method and Circuit for Protecting a DRAM Memory Device from the Row Hammer Effect. U.S. Patent: 10 885 966."},{"key":"e_1_3_3_2_37_2","volume-title":"NAACL","author":"Devlin Jacob","year":"2019","unstructured":"Jacob Devlin, Ming-Wei Chang, Kenton Lee, and Kristina Toutanova. 2019. BERT: Pre-training of Deep Bidirectional Transformers for Language Understanding. In NAACL."},{"key":"e_1_3_3_2_38_2","doi-asserted-by":"publisher","DOI":"10.14722\/ndss.2023.24337"},{"key":"e_1_3_3_2_39_2","unstructured":"DSN 2024. 2024. The Jean-Claude Laprie Award. https:\/\/dsn2024uq.github.io\/awards_jcl.html."},{"key":"e_1_3_3_2_40_2","unstructured":"DSN 2025. 2025. DSN 2025 Test of Time Award. https:\/\/dsn2025.github.io\/awards_tft.html."},{"key":"e_1_3_3_2_41_2","unstructured":"DSN 2026. 2026. DSN 2026 Test of Time Award. https:\/\/dsn2026.github.io\/awards_tft.html."},{"key":"e_1_3_3_2_42_2","doi-asserted-by":"crossref","unstructured":"Shuhei Enomoto Hiroki Kuzuno and Hiroshi Yamada. 2022. Efficient Protection Mechanism for CPU Cache Flush Instruction Based Attacks. IEICE TIS (2022).","DOI":"10.1587\/transinf.2022NGP0008"},{"key":"e_1_3_3_2_43_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA53966.2022.00035"},{"key":"e_1_3_3_2_44_2","doi-asserted-by":"publisher","DOI":"10.1109\/ETS50041.2021.9465436"},{"key":"e_1_3_3_2_45_2","doi-asserted-by":"publisher","DOI":"10.14722\/ndss.2026.230156"},{"key":"e_1_3_3_2_46_2","volume-title":"CHES","author":"France Lo\u00efc","year":"2022","unstructured":"Lo\u00efc France, Florent Bruguier, Maria Mushtaq, David Novo, and Pascal Benoit. 2022. Modeling Rowhammer in the gem5 Simulator. In CHES."},{"key":"e_1_3_3_2_47_2","doi-asserted-by":"crossref","unstructured":"Lo\u00efc France Florent Bruguier David Novo Maria Mushtaq and Pascal Benoit. 2023. Reducing the Silicon Area Overhead of Counter-Based Rowhammer Mitigations. IEEE CAL (2023).","DOI":"10.1109\/LCA.2023.3328824"},{"key":"e_1_3_3_2_48_2","doi-asserted-by":"publisher","DOI":"10.1109\/SP40000.2020.00090"},{"key":"e_1_3_3_2_49_2","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358260"},{"key":"e_1_3_3_2_50_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO56248.2022.00066"},{"key":"e_1_3_3_2_51_2","doi-asserted-by":"crossref","unstructured":"Esteban Garz\u00f3n Alexander Fish and Leonid Yavits. 2026. CADM: Content Addressable Commodity Off-the-Shelf DRAM-based Genome Classifier. Journal of Systems Architecture (2026).","DOI":"10.1016\/j.sysarc.2026.103710"},{"key":"e_1_3_3_2_52_2","unstructured":"Saugata Ghose Amirali Boroumand Jeremie\u00a0S Kim Juan G\u00f3mez-Luna and Onur Mutlu. 2019. Processing-in-Memory: A Workload-driven Perspective. IBM JRD (2019)."},{"key":"e_1_3_3_2_53_2","doi-asserted-by":"publisher","DOI":"10.1145\/3219617.3219661"},{"key":"e_1_3_3_2_54_2","unstructured":"Zvika Greenfield and Tomer Levy. 2016. Throttling Support for Row-Hammer Counters. U.S. Patent 9 251 885."},{"key":"e_1_3_3_2_55_2","unstructured":"C Gude\u00a0Ramarao K\u00a0Tejesh Kumar G Ujjinappa and B\u00a0Vasu\u00a0Deva Naidu. 2023. Defending SoCs with FPGAs from Rowhammer Attacks. Material Science (2023)."},{"key":"e_1_3_3_2_56_2","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID2022.2022.00053"},{"key":"e_1_3_3_2_57_2","doi-asserted-by":"crossref","unstructured":"Juan G\u00f3mez-Luna Izzat\u00a0El Hajj Ivan Fernandez Christina Giannoula Geraldo\u00a0F. Oliveira and Onur Mutlu. 2022. Benchmarking a New Paradigm: Experimental Analysis and Characterization of a Real Processing-in-Memory System. IEEE Access (2022).","DOI":"10.1109\/ACCESS.2022.3174101"},{"key":"e_1_3_3_2_58_2","unstructured":"Jin-Woo Han Jungsik Kim Dafna Beery K.\u00a0Deniz Bozdag Peter Cuevas Amitay Levi Irwin Tain Khai Tran Andrew\u00a0J. Walker Senthil\u00a0Vadakupudhu Palayam Antonio Arreghini Arnaud Furn\u00e9mont and M. Meyyappan. 2021. Surround Gate Transistor With Epitaxially Grown Si Pillar and Simulation Study on Soft Error and Rowhammer Tolerance for DRAM. IEEE TED (2021)."},{"key":"e_1_3_3_2_59_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO61859.2024.00074"},{"key":"e_1_3_3_2_60_2","volume-title":"MICRO","author":"Hassan Hasan","year":"2021","unstructured":"Hasan Hassan, Yahya\u00a0Can Tugrul, Jeremie\u00a0S. Kim, Victor van\u00a0der Veen, Kaveh Razavi, and Onur Mutlu. 2021. Uncovering In-DRAM RowHammer Protection Mechanisms: A New Methodology, Custom RowHammer Patterns, and Implications. In MICRO."},{"key":"e_1_3_3_2_61_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.62"},{"key":"e_1_3_3_2_62_2","unstructured":"Hewlett-Packard Enterprise. 2015. HP Moonshot Component Pack Version 2015.05.0. http:\/\/h17007.www1.hp.com\/us\/en\/enterprise\/servers\/products\/moonshot\/component-pack\/index.aspx."},{"key":"e_1_3_3_2_63_2","unstructured":"Seungki Hong Dongha Kim Jaehyung Lee Reum Oh Changsik Yoo Sangjoon Hwang and Jooyoung Lee. 2023. DSAC: Low-Cost Rowhammer Mitigation Using In-DRAM Stochastic and Approximate Counting Algorithm. arXiv:2302.03591."},{"key":"e_1_3_3_2_64_2","unstructured":"ICCAD 2025. 2025. Top Picks in Hardware and Embedded Security. https:\/\/safari.ethz.ch\/revisiting-rowhammer-awarded-top-picks\/."},{"key":"e_1_3_3_2_65_2","unstructured":"Gorka Irazoqui Thomas Eisenbarth and Berk Sunar. 2016. MASCAT: Stopping Microarchitectural Attacks Before Execution. IACR Cryptology (2016)."},{"key":"e_1_3_3_2_66_2","volume-title":"ISCA","author":"Jaleel Aamer","year":"2024","unstructured":"Aamer Jaleel, Gururaj Saileshwar, Stephen\u00a0W. Keckler, and Moinuddin Qureshi. 2024. PrIDE: Achieving Secure Rowhammer Mitigation with Low-Cost In-DRAM Trackers. In ISCA."},{"key":"e_1_3_3_2_67_2","volume-title":"JESD79-5C: DDR5 SDRAM Standard","year":"2024","unstructured":"JEDEC. 2024. JESD79-5C: DDR5 SDRAM Standard."},{"key":"e_1_3_3_2_68_2","doi-asserted-by":"publisher","DOI":"10.1109\/IMW68301.2026.11532903"},{"key":"e_1_3_3_2_69_2","volume-title":"DATE","author":"Joardar Biresh\u00a0Kumar","year":"2022","unstructured":"Biresh\u00a0Kumar Joardar, Tyler\u00a0K Bletsch, and Krishnendu Chakrabarty. 2022. Learning to Mitigate RowHammer Attacks. In DATE."},{"key":"e_1_3_3_2_70_2","doi-asserted-by":"crossref","unstructured":"Biresh\u00a0Kumar Joardar Tyler\u00a0K. Bletsch and Krishnendu Chakrabarty. 2022. Machine Learning-based Rowhammer Mitigation. TCAD (2022).","DOI":"10.7924\/r4hh6p604"},{"key":"e_1_3_3_2_71_2","volume-title":"ISCA","author":"Jouppi Norm","year":"2023","unstructured":"Norm Jouppi, George Kurian, Sheng Li, Peter Ma, Rahul Nagarajan, Lifeng Nai, Nishant Patil, Suvinay Subramanian, Andy Swing, Brian Towles, Clifford Young, Xiang Zhou, Zongwei Zhou, and David\u00a0A Patterson. 2023. TPU v4: An Optically Reconfigurable Supercomputer for Machine Learning with Hardware Support for Embeddings. In ISCA."},{"key":"e_1_3_3_2_72_2","volume-title":"S&P","author":"Juffinger Jonas","year":"2023","unstructured":"Jonas Juffinger, Lukas Lamster, Andreas Kogler, Maria Eichlseder, Moritz Lipp, and Daniel Gruss. 2023. CSI: Rowhammer\u2013Cryptographic Security and Integrity against Rowhammer. In S&P."},{"key":"e_1_3_3_2_73_2","volume-title":"ISCA","author":"Kakolyris Andreas\u00a0Kosmas","year":"2026","unstructured":"Andreas\u00a0Kosmas Kakolyris, F.\u00a0Nisa Bostanci, Ataberk Olgun, Ismail\u00a0Emir Yuksel, Harsh Songara, Konstantinos\u00a0Marios Sgouras, Umut Baser, Konstantinos Kanellopoulos, A.\u00a0Giray Yaglikci, and Onur Mutlu. 2026. ColumnKeeper: Efficient Solutions for Mitigating ColumnDisturb in DRAM-based Systems. In ISCA."},{"key":"e_1_3_3_2_74_2","doi-asserted-by":"crossref","unstructured":"Ingab Kang Eojin Lee and Jung\u00a0Ho Ahn. 2020. CAT-TWO: Counter-Based Adaptive Tree Time Window Optimized for DRAM Row-Hammer Prevention. IEEE Access (2020).","DOI":"10.1109\/ACCESS.2020.2967217"},{"key":"e_1_3_3_2_75_2","doi-asserted-by":"publisher","DOI":"10.1145\/2591971.2592000"},{"key":"e_1_3_3_2_76_2","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2016.30"},{"key":"e_1_3_3_2_77_2","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3123945"},{"key":"e_1_3_3_2_78_2","unstructured":"Dae-Hyun Kim Prashant\u00a0J Nair and Moinuddin\u00a0K Qureshi. 2014. Architectural Support for Mitigating Row Hammering in DRAM Memories. IEEE CAL (2014)."},{"key":"e_1_3_3_2_79_2","volume-title":"ISCA","author":"Kim Jumin","year":"2026","unstructured":"Jumin Kim, Seungmin Baek, Hwayong Nam, Minbok Wi, Nam\u00a0Sung Kim, and Jung\u00a0Ho Ahn. 2026. PVAC: A RowHammer Mitigation Architecture Exploiting Per-victim-row Counting. In ISCA."},{"key":"e_1_3_3_2_80_2","doi-asserted-by":"crossref","unstructured":"Jumin Kim Seungmin Baek Minbok Wi Hwayong Nam Michael\u00a0Jaemin Kim Sukhan Lee Kyomin Sohn and Jung\u00a0Ho Ahn. 2025. Per-Row Activation Counting on Real Hardware: Demystifying Performance Overheads. IEEE CAL (2025).","DOI":"10.1109\/LCA.2025.3587293"},{"key":"e_1_3_3_2_81_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2018.00026"},{"key":"e_1_3_3_2_82_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2019.00011"},{"key":"e_1_3_3_2_83_2","volume-title":"ISCA","author":"Kim Jeremie\u00a0S.","year":"2020","unstructured":"Jeremie\u00a0S. Kim, Minesh Patel, Abdullah\u00a0Giray Ya\u011fl\u0131kc\u0131, Hasan Hassan, Roknoddin Azizi, Lois Orosa, and Onur Mutlu. 2020. Revisiting RowHammer: An Experimental Analysis of Modern Devices and Mitigation Techniques. In ISCA."},{"key":"e_1_3_3_2_84_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA53966.2022.00088"},{"key":"e_1_3_3_2_85_2","doi-asserted-by":"publisher","DOI":"10.1145\/3613424.3623777"},{"key":"e_1_3_3_2_86_2","volume-title":"ISSCC","author":"Kim Woongrae","year":"2023","unstructured":"Woongrae Kim, Chulmoon Jung, Seongnyuh Yoo, Duckhwa Hong, Jeongjin Hwang, Jungmin Yoon, Ohyong Jung, Joonwoo Choi, Sanga Hyun, Mankeun Kang, et\u00a0al. 2023. A 1.1 V 16Gb DDR5 DRAM with Probabilistic-Aggressor Tracking, Refresh-Management Functionality, Per-Row Hammer Tracking, a Multi-Step Precharge, and Core-Bias Modulation for Security and Reliability Enhancement. In ISSCC."},{"key":"e_1_3_3_2_87_2","doi-asserted-by":"crossref","unstructured":"Yoongu Kim et\u00a0al. 2016. Ramulator: A Fast and Extensible DRAM Simulator. CAL (2016).","DOI":"10.1109\/LCA.2015.2414456"},{"key":"e_1_3_3_2_88_2","volume-title":"ISCA","author":"Kim Y.","year":"2014","unstructured":"Y. Kim, R. Daly, J. Kim, C. Fallin, J.\u00a0H. Lee, D. Lee, C. Wilkerson, K. Lai, and O. Mutlu. 2014. Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors. In ISCA."},{"key":"e_1_3_3_2_89_2","volume-title":"OSDI","author":"Konoth Radhesh\u00a0Krishnan","year":"2018","unstructured":"Radhesh\u00a0Krishnan Konoth, Marco Oliverio, Andrei Tatar, Dennis Andriesse, Herbert Bos, Cristiano Giuffrida, and Kaveh Razavi. 2018. ZebRAM: Comprehensive and Compatible Software Protection Against Rowhammer Attacks. In OSDI."},{"key":"e_1_3_3_2_90_2","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358280"},{"key":"e_1_3_3_2_91_2","doi-asserted-by":"crossref","unstructured":"Tatsuya Kubo Daichi Tokuda Lei Qu Ting Cao and Shinya Takamaeda-Yamazaki. 2025. PUDTune: Multi-Level Charging for High-Precision Calibration in Processing-Using-DRAM. IEEE CAL (2025).","DOI":"10.1109\/LCA.2025.3585312"},{"key":"e_1_3_3_2_92_2","volume-title":"DRAMSec","author":"Lang Zhenrong","year":"2023","unstructured":"Zhenrong Lang, Patrick Jattke, Michele Marazzi, and Kaveh Razavi. 2023. BLASTER: Characterizing the Blast Radius of Rowhammer. In DRAMSec."},{"key":"e_1_3_3_2_93_2","unstructured":"Donghyuk Lee Saugata Ghose Gennady Pekhimenko Samira Khan and Onur Mutlu. 2016. Simultaneous Multi-Layer Access: Improving 3D-Stacked Memory Bandwidth at Low Cost. TACO (2016)."},{"key":"e_1_3_3_2_94_2","volume-title":"ISCA","author":"Lee Eojin","year":"2019","unstructured":"Eojin Lee, Ingab Kang, Sukhan Lee, G.\u00a0Edward Suh, and Jung\u00a0Ho Ahn. 2019. TWiCe: Preventing Row-Hammering by Exploiting Time Window Counters. In ISCA."},{"key":"e_1_3_3_2_95_2","volume-title":"ISCA","author":"Lee Gyu-Hyeon","year":"2021","unstructured":"Gyu-Hyeon Lee, Seongmin Na, Ilkwon Byun, Dongmoon Min, and Jangwoo Kim. 2021. CryoGuard: A Near Refresh-Free Robust DRAM Design for Cryogenic Computing. In ISCA."},{"key":"e_1_3_3_2_96_2","unstructured":"Lenovo. 2015. Row Hammer Privilege Escalation. https:\/\/support.lenovo.com\/us\/en\/product_security\/row_hammer."},{"key":"e_1_3_3_2_97_2","volume-title":"ISCA","author":"Liu Jamie","year":"2013","unstructured":"Jamie Liu, Ben Jaiyen, Yoongu Kim, Chris Wilkerson, Onur Mutlu, J Liu, B Jaiyen, Y Kim, C Wilkerson, and O Mutlu. 2013. An Experimental Study of Data Retention Behavior in Modern DRAM Devices. In ISCA."},{"key":"e_1_3_3_2_98_2","doi-asserted-by":"publisher","DOI":"10.1145\/3458336.3465295"},{"key":"e_1_3_3_2_99_2","volume-title":"ISCA","author":"Loughlin Kevin","year":"2022","unstructured":"Kevin Loughlin, Stefan Saroiu, Alec Wolman, Yatin\u00a0A. Manerkar, and Baris Kasikci. 2022. MOESI-Prime: Preventing Coherence-Induced Hammering in Commodity Workloads. In ISCA."},{"key":"e_1_3_3_2_100_2","unstructured":"Haocong Luo F.\u00a0Nisa Bostanc\u0131 Ataberk Olgun Maria Makeenkova Ziad Malik Ipek Akdeniz and Onur Mutlu. 2026. Ramulator 2.1: A Composable Memory System Simulator for Modern DRAM Systems. The 3rd Tutorial on Ramulator and DRAM Bender colocated with ICS."},{"key":"e_1_3_3_2_101_2","volume-title":"ISCA","author":"Luo Haocong","year":"2023","unstructured":"Haocong Luo, Ataberk Olgun, Abdullah\u00a0Giray Ya\u011fl\u0131kc\u0131, Yahya\u00a0Can Tu\u011frul, Steve Rhyner, Meryem\u00a0Banu Cavlak, Jo\u00ebl Lindegger, Mohammad Sadrosadati, and Onur Mutlu. 2023. RowPress: Amplifying Read Disturbance in Modern DRAM Chips. In ISCA."},{"key":"e_1_3_3_2_102_2","unstructured":"Haocong Luo Yahya\u00a0Can Tugrul F.\u00a0Nisa Bostanci Ataberk Olgun Abdullah\u00a0Giray Yaglikci and Onur Mutlu. 2024. Ramulator 2.0: A Modern Modular and Extensible DRAM Simulator. IEEE CAL (2024)."},{"key":"e_1_3_3_2_103_2","volume-title":"ISCA","author":"Luo Haocong","year":"2026","unstructured":"Haocong Luo, Ismail\u00a0Emir Y\u00fcksel, Ataberk Olgun, Nisa Bostanci, Orhun Ecemis, Abdullah\u00a0Giray Ya\u011fl\u0131k\u00e7\u0131, and Onur Mutlu. 2026. DejaVu: Why You Should Write to Your DRAM Rows Twice, Carefully. In ISCA."},{"key":"e_1_3_3_2_104_2","doi-asserted-by":"publisher","DOI":"10.1109\/VTS65138.2025.11022861"},{"key":"e_1_3_3_2_105_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO56248.2022.00020"},{"key":"e_1_3_3_2_106_2","volume-title":"S&P","author":"Marazzi Michele","year":"2022","unstructured":"Michele Marazzi, Patrick Jattke, Flavien Solt, and Kaveh Razavi. 2022. REGA: Scalable Rowhammer Mitigation with Refresh-Generating Activations. In S&P."},{"key":"e_1_3_3_2_107_2","volume-title":"S&P","author":"Marazzi Michele","year":"2023","unstructured":"Michele Marazzi, Flavien Solt, Patrick Jattke, Kubo Takashi, and Kaveh Razavi. 2023. ProTRR: Principled yet Optimal In-DRAM Target Row Refresh. In S&P."},{"key":"e_1_3_3_2_108_2","unstructured":"Jos\u00e9\u00a0F. Mart\u00ednez Engin Ipek Onur Mutlu and Rich Caruana. 2023. Retrospective: Self-optimizing Memory Controllers: A Reinforcement Learning Approach. Retrospective Issue for ISCA-50."},{"key":"e_1_3_3_2_109_2","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2013.6582088"},{"key":"e_1_3_3_2_110_2","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4939-2163-8_6"},{"key":"e_1_3_3_2_111_2","volume-title":"DATE","author":"Mutlu Onur","year":"2017","unstructured":"Onur Mutlu. 2017. The RowHammer Problem and Other Issues We May Face as Memory Becomes Denser. In DATE."},{"key":"e_1_3_3_2_112_2","volume-title":"DATE","author":"Mutlu Onur","year":"2021","unstructured":"Onur Mutlu. 2021. Intelligent Architectures for Intelligent Computing Systems. In DATE."},{"key":"e_1_3_3_2_113_2","volume-title":"ISCA@50 25-Year Retrospective: 1996-2020","author":"Mutlu Onur","year":"2023","unstructured":"Onur Mutlu. 2023. Retrospective: An Experimental Study of Data Retention Behavior in Modern DRAM Devices: Implications for Retention Time Profiling Mechanisms. In ISCA@50 25-Year Retrospective: 1996-2020."},{"key":"e_1_3_3_2_114_2","volume-title":"ISCA@50 25-Year Retrospective: 1996-2020","author":"Mutlu Onur","year":"2023","unstructured":"Onur Mutlu. 2023. Retrospective: Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors. In ISCA@50 25-Year Retrospective: 1996-2020."},{"key":"e_1_3_3_2_115_2","doi-asserted-by":"crossref","unstructured":"O. Mutlu et\u00a0al. 2019. Processing Data Where It Makes Sense: Enabling In-Memory Computation. MicPro (2019).","DOI":"10.1145\/3299874.3322805"},{"key":"e_1_3_3_2_116_2","unstructured":"Onur Mutlu Saugata Ghose Juan G\u00f3mez-Luna and Rachata Ausavarungnirun. 2025. A Modern Primer on Processing in Memory. arXiv:2012.03112 [cs.AR]."},{"key":"e_1_3_3_2_117_2","unstructured":"Onur Mutlu and Jeremie Kim. 2019. RowHammer: A Retrospective. IEEE TCAD Special Issue on Top Picks in Hardware and Embedded Security (2019)."},{"key":"e_1_3_3_2_118_2","volume-title":"IEDM","author":"Mutlu Onur","year":"2024","unstructured":"Onur Mutlu, Ataberk Olgun, Geraldo\u00a0F Oliveira, and Ismail\u00a0E Yuksel. 2024. Memory-Centric Computing: Recent Advances in Processing-in-DRAM. In IEDM."},{"key":"e_1_3_3_2_119_2","doi-asserted-by":"publisher","DOI":"10.1145\/3566097.3568350"},{"key":"e_1_3_3_2_120_2","doi-asserted-by":"publisher","DOI":"10.1109\/IMW61990.2025.11026935"},{"key":"e_1_3_3_2_121_2","unstructured":"Onur Mutlu and Lavanya Subramanian. 2014. Research Problems and Opportunities in Memory Systems. SUPERFRI (2014)."},{"key":"e_1_3_3_2_122_2","unstructured":"Hwayong Nam Seungmin Baek Minbok Wi Michael\u00a0Jaemin Kim Jaehyun Park Chihun Song Nam\u00a0Sung Kim and Jung\u00a0Ho Ahn. 2023. X-Ray: Discovering DRAM Internal Structure and Error Characteristics by Issuing Memory Commands. IEEE CAL (2023)."},{"key":"e_1_3_3_2_123_2","volume-title":"ISCA","author":"Nam Hwayong","year":"2024","unstructured":"Hwayong Nam, Seungmin Baek, Minbok Wi, Michael\u00a0Jaemin Kim, Jaehyun Park, Chihun Song, Nam\u00a0Sung Kim, and Jung\u00a0Ho Ahn. 2024. DRAMScope: Uncovering DRAM Microarchitecture and Characteristics by Issuing Memory Commands. In ISCA."},{"key":"e_1_3_3_2_124_2","doi-asserted-by":"crossref","unstructured":"Amir Naseredini Martin Berger Matteo Sammartino and Shale Xiong. 2022. ALARM: Active LeArning of Rowhammer Mitigations. https:\/\/users.sussex.ac.uk\/\u00a0mfb21\/rh-draft.pdf.","DOI":"10.1145\/3569562.3569563"},{"key":"e_1_3_3_2_125_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA61900.2025.00069"},{"key":"e_1_3_3_2_126_2","doi-asserted-by":"crossref","unstructured":"Ataberk Olgun Hasan Hassan A.\u00a0Giray Ya\u011fl\u0131kc\u0131 Yahya\u00a0Can Tu\u011frul Lois Orosa Haocong Luo Minesh Patel Ergin O\u011fuz and Onur Mutlu. 2023. DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chips. TCAD (2023).","DOI":"10.1109\/TCAD.2023.3282172"},{"key":"e_1_3_3_2_127_2","doi-asserted-by":"crossref","unstructured":"Ataberk Olgun Juan\u00a0Gomez Luna Konstantinos Kanellopoulos Behzad Salami Hasan Hassan Oguz Ergin and Onur Mutlu. 2022. PiDRAM: A Holistic End-to-End FPGA-Based Framework for Processing-in-DRAM. TACO (2022).","DOI":"10.1145\/3563697"},{"key":"e_1_3_3_2_128_2","doi-asserted-by":"publisher","DOI":"10.1109\/DSN-S58398.2023.00042"},{"key":"e_1_3_3_2_129_2","doi-asserted-by":"publisher","DOI":"10.1109\/DSN58291.2024.00022"},{"key":"e_1_3_3_2_130_2","volume-title":"ISCA","author":"Olgun Ataberk","year":"2021","unstructured":"Ataberk Olgun, Minesh Patel, A\u00a0Giray Ya\u011fl\u0131k\u00e7\u0131, Haocong Luo, Jeremie\u00a0S Kim, F\u00a0Nisa Bostanc\u0131, Nandita Vijaykumar, O\u011fuz Ergin, and Onur Mutlu. 2021. QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips. In ISCA."},{"key":"e_1_3_3_2_131_2","volume-title":"USENIX Security","author":"Olgun Ataberk","year":"2024","unstructured":"Ataberk Olgun, Yahya\u00a0Can Tugrul, Nisa Bostanci, Ismail\u00a0Emir Yuksel, Haocong Luo, Steve Rhyner, Abdullah\u00a0Giray Yaglikci, Geraldo\u00a0F. Oliveira, and Onur Mutlu. 2024. ABACuS: All-Bank Activation Counters for Scalable and Low Overhead RowHammer Mitigation. In USENIX Security."},{"key":"e_1_3_3_2_132_2","doi-asserted-by":"crossref","unstructured":"Geraldo\u00a0F. Oliveira Juan G\u00f3mez-Luna Saugata Ghose Amirali Boroumand and Onur Mutlu. 2022. Accelerating Neural Network Inference With Processing-in-DRAM: From the Edge to the Cloud. IEEE Micro (2022).","DOI":"10.1109\/MM.2022.3202350"},{"key":"e_1_3_3_2_133_2","doi-asserted-by":"crossref","unstructured":"Geraldo\u00a0F. Oliveira Juan G\u00f3mez-Luna Lois Orosa Saugata Ghose Nandita Vijaykumar Ivan Fernandez Mohammad Sadrosadati and Onur Mutlu. 2021. DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks. IEEE Access (2021).","DOI":"10.1109\/ACCESS.2021.3110993"},{"key":"e_1_3_3_2_134_2","doi-asserted-by":"crossref","unstructured":"Lois Orosa Ulrich R\u00fchrmair A\u00a0Giray Yaglikci Haocong Luo Ataberk Olgun Patrick Jattke Minesh Patel Jeremie Kim Kaveh Razavi and Onur Mutlu. 2024. SpyHammer: Understanding and Exploiting RowHammer Under Fine-Grained Temperature Variations. IEEE Access (2024).","DOI":"10.1109\/ACCESS.2024.3409389"},{"key":"e_1_3_3_2_135_2","volume-title":"ISCA","author":"Orosa Lois","year":"2021","unstructured":"Lois Orosa, Yaohua Wang, Mohammad Sadrosadati, Jeremie\u00a0S Kim, Minesh Patel, Ivan Puddu, Haocong Luo, Kaveh Razavi, Juan G\u00f3mez-Luna, Hasan Hassan, et\u00a0al. 2021. CODIC: A Low-Cost Substrate for Enabling Custom In-DRAM Functionalities and Optimizations. In ISCA."},{"key":"e_1_3_3_2_136_2","volume-title":"MICRO","author":"Orosa Lois","year":"2021","unstructured":"Lois Orosa, A\u00a0Giray Ya\u011fl\u0131kc\u0131, Haocong Luo, Ataberk Olgun, Jisung Park, Hasan Hassan, Minesh Patel, Jeremie\u00a0S. Kim, and Onur Mutlu. 2021. A Deeper Look into RowHammer\u2019s Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses. In MICRO."},{"key":"e_1_3_3_2_137_2","doi-asserted-by":"crossref","unstructured":"Jin\u00a0Hyo Park Su\u00a0Yeon Kim Dong\u00a0Young Kim Geon Kim Je\u00a0Won Park Sunyong Yoo Young-Woo Lee and Myoung\u00a0Jin Lee. 2022. RowHammer Reduction Using a Buried Insulator in a Buried Channel Array Transistor. IEEE TED (2022).","DOI":"10.1109\/TED.2022.3215931"},{"key":"e_1_3_3_2_138_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO50266.2020.00014"},{"key":"e_1_3_3_2_139_2","volume-title":"MICRO","author":"Patel Minesh","year":"2021","unstructured":"Minesh Patel, Geraldo\u00a0Francisco de Oliveira\u00a0Jr., and Onur Mutlu. 2021. HARP: Practically and Effectively Identifying Uncorrectable Errors in Main Memory Chips That Use On-Die ECC. In MICRO."},{"key":"e_1_3_3_2_140_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO50266.2020.00034"},{"key":"e_1_3_3_2_141_2","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2019.00017"},{"key":"e_1_3_3_2_142_2","volume-title":"ISCA","author":"Patel Minesh","year":"2017","unstructured":"Minesh Patel, Jeremie\u00a0S Kim, and Onur Mutlu. 2017. The Reach Profiler (REAPER): Enabling the Mitigation of DRAM Retention Failures via Profiling at Aggressive Conditions. In ISCA."},{"key":"e_1_3_3_2_143_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA68181.2026.11408602"},{"key":"e_1_3_3_2_144_2","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2015.58"},{"key":"e_1_3_3_2_145_2","volume-title":"ISCA","author":"Qureshi Moinuddin\u00a0K.","year":"2022","unstructured":"Moinuddin\u00a0K. Qureshi, Aditya Rohan, Gururaj Saileshwar, and Prashant\u00a0J Nair. 2022. Hydra: Enabling Low-Overhead Mitigation of Row-Hammer at Ultra-Low Thresholds via Hybrid Tracking. In ISCA."},{"key":"e_1_3_3_2_146_2","unstructured":"SAFARI Research Group. 2017. SoftMC \u2014 GitHub Repository. https:\/\/github.com\/CMU-SAFARI\/SoftMC."},{"key":"e_1_3_3_2_147_2","unstructured":"SAFARI Research Group. 2018. VAMPIRE \u2014 GitHub Repository. https:\/\/github.com\/CMU-SAFARI\/VAMPIRE."},{"key":"e_1_3_3_2_148_2","unstructured":"SAFARI Research Group. 2021. Ramulator \u2014 GitHub Repository. https:\/\/github.com\/CMU-SAFARI\/ramulator."},{"key":"e_1_3_3_2_149_2","unstructured":"SAFARI Research Group. 2022. DRAM Bender \u2014 GitHub Repository. https:\/\/github.com\/CMU-SAFARI\/DRAM-Bender."},{"key":"e_1_3_3_2_150_2","unstructured":"SAFARI Research Group. 2022. P&S DRAM Bender: Fall 2022 Playlist. https:\/\/www.youtube.com\/watch?v=pJLo3kmVx6M&list=PL5Q2soXY2Zi9x75UW78ulmpzQ3W6whmAZ."},{"key":"e_1_3_3_2_151_2","unstructured":"SAFARI Research Group. 2022. P&S DRAM Bender: Spring 2022 Introduction. https:\/\/www.youtube.com\/watch?v=r5QxuoJWttg."},{"key":"e_1_3_3_2_152_2","unstructured":"SAFARI Research Group. 2023. P&S DRAM Bender: Spring 2023 Introduction. https:\/\/youtu.be\/cfALQpemP5A."},{"key":"e_1_3_3_2_153_2","unstructured":"SAFARI Research Group. 2023. Ramulator 2.0 \u2014 GitHub Repository. https:\/\/github.com\/CMU-SAFARI\/ramulator2."},{"key":"e_1_3_3_2_154_2","unstructured":"SAFARI Research Group. 2024. P&S DRAM Bender: Fall\/Spring 2024 Playlist. https:\/\/www.youtube.com\/watch?v=MS30ZVRKT6M&list=PLnSFDsUEfGz79vy8y2i18113yhj1q3FGf."},{"key":"e_1_3_3_2_155_2","unstructured":"SAFARI Research Group. 2025. P&S DRAM Bender: Spring 2025 Course Page. https:\/\/safari.ethz.ch\/projects_and_seminars\/spring2025\/doku.php?id=dram_bender."},{"key":"e_1_3_3_2_156_2","unstructured":"SAFARI Research Group. 2026. 2nd Ramulator & DRAM Bender Tutorial at ISCA 2026. https:\/\/events.safari.ethz.ch\/isca26-ramulator-drambender\/."},{"key":"e_1_3_3_2_157_2","unstructured":"SAFARI Research Group. 2026. 3rd Ramulator & DRAM Bender Tutorial at ICS 2026. https:\/\/events.safari.ethz.ch\/ics26-ramulator-drambender\/."},{"key":"e_1_3_3_2_158_2","unstructured":"SAFARI Research Group. 2026. Ramulator & DRAM Bender Tutorial at ASPLOS 2026. https:\/\/events.safari.ethz.ch\/asplos26-ramulator-drambender\/."},{"key":"e_1_3_3_2_159_2","doi-asserted-by":"publisher","DOI":"10.1145\/3503222.3507716"},{"key":"e_1_3_3_2_160_2","unstructured":"Stefan Saroiu. [n. d.]. DDR5 Spec Update Has All It Needs to End Rowhammer: Will It? https:\/\/stefan.t8k2.com\/rh\/PRAC\/index.html."},{"key":"e_1_3_3_2_161_2","unstructured":"Stefan Saroiu and Alec Wolman. 2022. How to Configure Row-Sampling-Based Rowhammer Defenses. DRAMSec (2022)."},{"key":"e_1_3_3_2_162_2","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS48227.2022.9764591"},{"key":"e_1_3_3_2_163_2","doi-asserted-by":"publisher","DOI":"10.1145\/3620665.3640404"},{"key":"e_1_3_3_2_164_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA57654.2024.00049"},{"key":"e_1_3_3_2_165_2","doi-asserted-by":"publisher","DOI":"10.1109\/DSN58367.2023.00022"},{"key":"e_1_3_3_2_166_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO56248.2022.00022"},{"key":"e_1_3_3_2_167_2","doi-asserted-by":"crossref","unstructured":"Vivek Seshadri Kevin Hsieh Amirali Boroum Donghyuk Lee Michael\u00a0A Kozuch Onur Mutlu Phillip\u00a0B Gibbons and Todd\u00a0C Mowry. 2015. Fast Bulk Bitwise AND and OR in DRAM. IEEE Computer Architecture Letters (2015).","DOI":"10.1109\/LCA.2015.2434872"},{"key":"e_1_3_3_2_168_2","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540725"},{"key":"e_1_3_3_2_169_2","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3124544"},{"key":"e_1_3_3_2_170_2","unstructured":"Vivek Seshadri and Onur Mutlu. 2020. In-DRAM Bulk Bitwise Execution Engine."},{"key":"e_1_3_3_2_171_2","volume-title":"ISCA","author":"Seyedzadeh S.\u00a0M.","year":"2018","unstructured":"S.\u00a0M. Seyedzadeh, A.\u00a0K. Jones, and R. Melhem. 2018. Mitigating Wordline Crosstalk Using Adaptive Trees of Counters. In ISCA."},{"key":"e_1_3_3_2_172_2","unstructured":"Sonia Sharma Debdeep Sanyal Arpit Mukhopadhyay and Ramij\u00a0Hasan Shaik. 2022. A Review on Study of Defects of DRAM-RowHammer and Its Mitigation. Journal For Basic Sciences (2022)."},{"key":"e_1_3_3_2_173_2","doi-asserted-by":"crossref","unstructured":"Gagandeep Singh Mohammed Alser Damla\u00a0Senol Cali Dionysios Diamantopoulos Juan G\u00f3mez-Luna Henk Corporaal and Onur Mutlu. 2021. FPGA-Based Near-Memory Acceleration of Modern Data-Intensive Applications. IEEE Micro (2021).","DOI":"10.1109\/MM.2021.3088396"},{"key":"e_1_3_3_2_174_2","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062281"},{"key":"e_1_3_3_2_175_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCE.2019.8662060"},{"key":"e_1_3_3_2_176_2","doi-asserted-by":"publisher","DOI":"10.1109\/HOST45689.2020.9300125"},{"key":"e_1_3_3_2_177_2","doi-asserted-by":"crossref","unstructured":"BMS\u00a0Bahar Talukder Biswajit Ray Domenic Forte and Md\u00a0Tauhidur Rahman. 2019. PreLatPUF: Exploiting DRAM Latency Variations for Generating Robust Device Signatures. IEEE Access (2019).","DOI":"10.1109\/ICCE.2019.8662060"},{"key":"e_1_3_3_2_178_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA68181.2026.11408571"},{"key":"e_1_3_3_2_179_2","volume-title":"ICS","author":"Tokuda Daichi","year":"2026","unstructured":"Daichi Tokuda, Tatsuya Kubo, Ismail\u00a0Emir Yuksel, Ataberk Olgun, Haocong Luo, Tomoya Nagatani, Geraldo F.\u00a0Oliveira, Abdullah\u00a0Giray Yaglikci, Mohammad Sadrosadati, Onur Mutlu, and Shinya Takamaeda-Yamazaki. 2026. Clutch: High Performance Vector-Scalar Comparison using DRAM via Chunked Temporal Coding. In ICS."},{"key":"e_1_3_3_2_180_2","volume-title":"ISCA","author":"Tokuda Daichi","year":"2026","unstructured":"Daichi Tokuda, Ismail\u00a0Emir Yuksel, Tatsuya Kubo, Ataberk Olgun, Haocong Luo, Nisa Bostanci, Jikun Wang, Abdullah\u00a0Giray Yaglikci, Shinya Takamaeda-Yamazaki, and Onur Mutlu. 2026. PuDGhost: Experimental Analysis of Computation Result Corruption in Processing-using-DRAM Operations on Real DRAM Chips and Implications for Future Systems. In ISCA."},{"key":"e_1_3_3_2_181_2","doi-asserted-by":"crossref","unstructured":"Chihiro Tomita Makoto Takita Kazuhide Fukushima Yuto Nakano Yoshiaki Shiraishi and Masakatu Morii. 2022. Extracting the Secrets of OpenSSL with RAMBleed. Sensors (2022).","DOI":"10.3390\/s22093586"},{"key":"e_1_3_3_2_182_2","volume-title":"HPCA","author":"Tugrul Yahya\u00a0Can","year":"2025","unstructured":"Yahya\u00a0Can Tugrul, A.\u00a0Giray Yaglikci, Ismail\u00a0Emir Yuksel, Ataberk Olgun, Oguzhan Canpolat, Nisa Bostanci, Mohammad Sadrosadati, Oguz Ergin, and Onur Mutlu. 2025. Understanding RowHammer Under Reduced Refresh Latency: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions. In HPCA."},{"key":"e_1_3_3_2_183_2","volume-title":"DIMVA","author":"Veen Victor van\u00a0der","year":"2018","unstructured":"Victor van\u00a0der Veen, Martina Lindorfer, Yanick Fratantonio, Harikrishnan\u00a0Padmanabha Pillai, Giovanni Vigna, Christopher Kruegel, Herbert Bos, and Kaveh Razavi. 2018. GuardION: Practical Mitigation of DMA-Based Rowhammer Attacks on ARM. In DIMVA."},{"key":"e_1_3_3_2_184_2","volume-title":"HASP","author":"Vig Saru","year":"2018","unstructured":"Saru Vig, Sarani Bhattacharya, Debdeep Mukhopadhyay, and Siew-Kei Lam. 2018. Rapid Detection of Rowhammer Attacks Using Dynamic Skewed Hash Tree. In HASP."},{"key":"e_1_3_3_2_185_2","volume-title":"ISCA","author":"Vittal Suhas","year":"2025","unstructured":"Suhas Vittal, Salman Qazi, Poulami Das, and Moinuddin Qureshi. 2025. MoPAC: Efficiently Mitigating RowHammer with Probabilistic Activation Counting. In ISCA."},{"key":"e_1_3_3_2_186_2","volume-title":"DSN","author":"Wang Jikun","year":"2026","unstructured":"Jikun Wang, Haocong Luo, Ataberk Olgun, Ismail\u00a0Emir Yuksel, A.\u00a0Giray Yaglikci, Yu Liang, F.\u00a0Nisa Bostanci, Mohammad Sadrosadati, and Onur Mutlu. 2026. ScaleDisturb: Exploiting Temporal Asymmetry to Amplify Read Disturbance in Modern DRAM Chips. In DSN."},{"key":"e_1_3_3_2_187_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA56546.2023.10070966"},{"key":"e_1_3_3_2_188_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA56546.2023.10070999"},{"key":"e_1_3_3_2_189_2","doi-asserted-by":"publisher","DOI":"10.1145\/3631882.3631886"},{"key":"e_1_3_3_2_190_2","unstructured":"A.\u00a0Giray Ya\u011fl\u0131kc\u0131 Jeremie\u00a0S. Kim Fabrice Devaux and Onur Mutlu. 2021. Security Analysis of the Silver Bullet Technique for RowHammer Prevention. arXiv:2106.07084."},{"key":"e_1_3_3_2_191_2","doi-asserted-by":"publisher","DOI":"10.1109\/DSN53405.2022.00054"},{"key":"e_1_3_3_2_192_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO56248.2022.00062"},{"key":"e_1_3_3_2_193_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA51647.2021.00037"},{"key":"e_1_3_3_2_194_2","volume-title":"HPCA","author":"Ya\u011fl\u0131kc\u0131 A.\u00a0Giray","year":"2024","unstructured":"A.\u00a0Giray Ya\u011fl\u0131kc\u0131, Yahya\u00a0Can Tu\u011frul, Geraldo\u00a0F De\u00a0Oliviera, Ismail\u00a0Emir Y\u00fcksel, Ataberk Olgun, Haocong Luo, and Onur Mutlu. 2024. Spatial Variation-Aware Read Disturbance Defenses: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions. In HPCA."},{"key":"e_1_3_3_2_195_2","doi-asserted-by":"publisher","DOI":"10.1007\/10968987_3"},{"key":"e_1_3_3_2_196_2","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317866"},{"key":"e_1_3_3_2_197_2","doi-asserted-by":"crossref","unstructured":"Ismail\u00a0Emir Yuksel F.\u00a0Nisa Bostanci Ataberk Olgun and Onur Mutlu. 2026. Memory-Centric Computing: Security Benefits and Challenges of Processing-in-DRAM. The 7th Workshop on Memory-Centric Computing Systems colocated with ICS.","DOI":"10.1145\/3774895.3819989"},{"key":"e_1_3_3_2_198_2","volume-title":"ICCD","author":"Yuksel Ismail\u00a0Emir","year":"2025","unstructured":"Ismail\u00a0Emir Yuksel, Ataberk Olgun, F Bostanci, Oguzhan Canpolat, Geraldo\u00a0F Oliveira, Mohammad Sadrosadati, Abdullah\u00a0Giray Yaglikci, and Onur Mutlu. 2025. In-DRAM True Random Number Generation Using Simultaneous Multiple-Row Activation: An Experimental Study of Real DRAM Chips. In ICCD."},{"key":"e_1_3_3_2_199_2","doi-asserted-by":"publisher","DOI":"10.1145\/3725843.3756022"},{"key":"e_1_3_3_2_200_2","volume-title":"ISCA","author":"Yuksel Ismail\u00a0Emir","year":"2025","unstructured":"Ismail\u00a0Emir Yuksel, Akash Sood, Ataberk Olgun, O\u011fuzhan Canpolat, Haocong Luo, Nisa Bostanci, Mohammad Sadrosadati, Giray Yaglikci, and Onur Mutlu. 2025. PuDHammer: Experimental Analysis of Read Disturbance Effects of Processing-using-DRAM in Real DRAM Chips. In ISCA."},{"key":"e_1_3_3_2_201_2","doi-asserted-by":"publisher","DOI":"10.1109\/DSN58291.2024.00024"},{"key":"e_1_3_3_2_202_2","unstructured":"Ismail\u00a0Emir Yuksel Yahya\u00a0Can Tugrul F.\u00a0Nisa Bostanci Abdullah\u00a0Giray Yaglikci Ataberk Olgun Geraldo\u00a0F. Oliveira Melina Soysal Haocong Luo Juan\u00a0Gomez Luna Mohammad Sadrosadati and Onur Mutlu. 2024. PULSAR: Simultaneous Many-Row Activation for Reliable and High-Performance Computing in Off-the-Shelf DRAM Chips. arXiv:2312.02880 [cs.AR]."},{"key":"e_1_3_3_2_203_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA57654.2024.00030"},{"key":"e_1_3_3_2_204_2","volume-title":"USENIX ATC","author":"Zhang Zhi","year":"2022","unstructured":"Zhi Zhang, Yueqiang Cheng, Minghua Wang, Wei He, Wenhao Wang, Surya Nepal, Yansong Gao, Kang Li, Zhe Wang, and Chenggang Wu. 2022. SoftTRR: Protect Page Tables against Rowhammer Attacks using Software-only Target Row Refresh. In USENIX ATC."},{"key":"e_1_3_3_2_205_2","doi-asserted-by":"publisher","DOI":"10.1109\/SP40000.2020.00060"},{"key":"e_1_3_3_2_206_2","doi-asserted-by":"crossref","unstructured":"Ranyang Zhou Sabbir Ahmed Adnan\u00a0Siraj Rakin and Shaahin Angizi. 2023. DNN-Defender: An in-DRAM Deep Neural Network Defense Mechanism for Adversarial Weight Attack. arXiv:2305.08034.","DOI":"10.1145\/3649329.3656222"},{"key":"e_1_3_3_2_207_2","volume-title":"DATE","author":"Zhou Ranyang","year":"2024","unstructured":"Ranyang Zhou, Sabbir Ahmed, Arman Roohi, Adnan\u00a0Siraj Rakin, and Shaahin Angizi. 2024. DRAM-Locker: A General-Purpose DRAM Protection Mechanism Against Adversarial DNN Weight Attacks. In DATE."},{"key":"e_1_3_3_2_208_2","volume-title":"DATE","author":"Zhou Ranyang","year":"2025","unstructured":"Ranyang Zhou, Jacqueline\u00a0T Liu, Sabbir Ahmed, Shaahin Angizi, and Adnan\u00a0Siraj Rakin. 2025. Compromising the Intelligence of Modern DNNs: On the Effectiveness of Targeted RowPress. In DATE."},{"key":"e_1_3_3_2_209_2","doi-asserted-by":"crossref","unstructured":"Ranyang Zhou Sepehr Tabrizchi Arman Roohi and Shaahin Angizi. 2022. LT-PIM: An LUT-Based Processing-in-DRAM Architecture With RowHammer Self-Tracking. IEEE CAL (2022).","DOI":"10.1109\/LCA.2022.3220084"}],"event":{"name":"ICS Workshops '26: 2026 International Conference on Supercomputing Workshops","location":"Belfast , Northern Ireland , United Kingdom","acronym":"ICS Workshops '26"},"container-title":["Proceedings of the 40th ACM International Conference on Supercomputing - Workshops"],"original-title":[],"deposited":{"date-parts":[[2026,7,4]],"date-time":"2026-07-04T10:24:13Z","timestamp":1783160653000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3774895.3820147"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,7,5]]},"references-count":208,"alternative-id":["10.1145\/3774895.3820147","10.1145\/3774895"],"URL":"https:\/\/doi.org\/10.1145\/3774895.3820147","relation":{},"subject":[],"published":{"date-parts":[[2026,7,5]]},"assertion":[{"value":"2026-07-05","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}