{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,27]],"date-time":"2026-05-27T15:02:51Z","timestamp":1779894171515,"version":"3.53.1"},"reference-count":39,"publisher":"Association for Computing Machinery (ACM)","issue":"2","funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"crossref","award":["No. 62472062, No. 62202079"],"award-info":[{"award-number":["No. 62472062, No. 62202079"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"crossref"}]},{"name":"Applied Basic Research Project of Liaoning Province","award":["2025JH2\/101330109"],"award-info":[{"award-number":["2025JH2\/101330109"]}]},{"DOI":"10.13039\/501100017683","name":"Dalian Science and technology Innovation Fund","doi-asserted-by":"crossref","award":["2024JJ12GX022"],"award-info":[{"award-number":["2024JJ12GX022"]}],"id":[{"id":"10.13039\/501100017683","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/501100012226","name":"Fundamental Research Funds for the Central Universities","doi-asserted-by":"crossref","award":["3132025265"],"award-info":[{"award-number":["3132025265"]}],"id":[{"id":"10.13039\/501100012226","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2026,6,30]]},"abstract":"<jats:p>\n                    As integrated circuit scale grows and design complexity rises, effective circuit representation helps support logic synthesis, formal verification, and other automated processes in electronic design automation. And-Inverter Graphs (AIGs), as a compact and canonical structure, are widely adopted for representing Boolean logic in these workflows. However, the increasing complexity and integration density of modern circuits introduce structural heterogeneity and global logic information loss in AIGs, posing significant challenges to accurate circuit modeling. To address these issues, we propose FuncGNN, which integrates hybrid feature aggregation to extract multi-granularity topological patterns, thereby mitigating structural heterogeneity and enhancing logic circuit representations. FuncGNN further introduces gate-aware normalization that adapts to circuit-specific gate distributions, improving robustness to structural heterogeneity. Finally, FuncGNN employs multi-layer integration to merge intermediate features across layers, effectively synthesizing local and global semantic information for comprehensive logic representations. Experimental results on two logic-level analysis tasks (i.e., signal probability prediction and truth-table distance prediction) demonstrate that FuncGNN outperforms existing state-of-the-art methods, achieving improvements of 2.06% and 18.71%, respectively, while reducing training time by approximately 50.6% and GPU memory usage by about 32.8%. The code is available at\n                    <jats:ext-link xmlns:xlink=\"http:\/\/www.w3.org\/1999\/xlink\" ext-link-type=\"uri\" xlink:href=\"https:\/\/github.com\/Vandbs\/FuncGNN\">https:\/\/github.com\/Vandbs\/FuncGNN<\/jats:ext-link>\n                    .\n                  <\/jats:p>","DOI":"10.1145\/3779445","type":"journal-article","created":{"date-parts":[[2025,12,5]],"date-time":"2025-12-05T14:42:40Z","timestamp":1764945760000},"page":"1-24","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["FuncGNN: Learning Functional Semantics of Logic Circuits with Graph Neural Networks"],"prefix":"10.1145","volume":"19","author":[{"ORCID":"https:\/\/orcid.org\/0009-0008-6698-8791","authenticated-orcid":false,"given":"Qiyun","family":"Zhao","sequence":"first","affiliation":[{"name":"Dalian Maritime University, Dalian, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8554-6365","authenticated-orcid":false,"given":"Shikai","family":"Guo","sequence":"additional","affiliation":[{"name":"Dalian Maritime University, Dalian, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0002-9728-3950","authenticated-orcid":false,"given":"Wen","family":"Zhao","sequence":"additional","affiliation":[{"name":"Dalian Maritime University, Dalian, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0004-3535-9758","authenticated-orcid":false,"given":"Ning","family":"Wang","sequence":"additional","affiliation":[{"name":"Chengdu Sino Microelectronics System Co. Ltd., Chengdu, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5068-1938","authenticated-orcid":false,"given":"Xiaochen","family":"Li","sequence":"additional","affiliation":[{"name":"Dalian University of Technology, Dalian, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8674-4948","authenticated-orcid":false,"given":"He","family":"Jiang","sequence":"additional","affiliation":[{"name":"Dalian University of Technology, Dalian, China"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2026,5,27]]},"reference":[{"key":"e_1_3_1_2_2","volume-title":"Proceedings of the International Workshop for Logic and Synthesis (IWLS)","volume":"9","author":"Albrecht Christoph","year":"2005","unstructured":"Christoph Albrecht. 2005. IWLS 2005 benchmarks. In Proceedings of the International Workshop for Logic and Synthesis (IWLS), Vol. 9. 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