{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,13]],"date-time":"2026-03-13T09:27:36Z","timestamp":1773394056028,"version":"3.50.1"},"reference-count":30,"publisher":"Association for Computing Machinery (ACM)","issue":"2","content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2026,3,31]]},"abstract":"<jats:p>\n                    The RISC-V architecture is increasingly deployed in safety-critical domains, such as automotive systems, yet the register file remains susceptible to Single Event Upsets (SEUs). Traditional fault-tolerance schemes like Triple Modular Redundancy (TMR) and Error Correction Codes (ECC) incur excessive area overhead (&gt;200%) or significant performance penalties (15.3\u201320.5% timing degradation), and critically, cannot prevent error accumulation. To address this, we propose\n                    <jats:bold>I-COR<\/jats:bold>\n                    , an instruction-level correction scheme that targets register file data errors. When an instruction accesses a corrupted register, I-COR replaces it with a corrective instruction pair: the first instruction rectifies the erroneous value through the write-back path to prevent error accumulation, while the second re-executes the original operation. By reusing existing forwarding paths, this pair maintains pipeline efficiency, introducing just one-cycle correction latency. Implemented on the Ibex core and synthesized in 28\u00a0nm, 110\u00a0nm CMOS, and 180\u00a0nm SOI technologies, I-COR reduces area overhead by 50.92\u201362.83% compared to TMR while avoiding ECC\u2019s timing degradation. Our automated two-stage fault-injection validation demonstrates I-COR\u2019s effectiveness: it achieves complete elimination of critical faults (0% occurrence for both application output mismatches and system hangs) and reduces non-critical faults (internal architectural errors without system-level impact) down to 0.12\u20133.17%, outperforming existing schemes by 2.6\u201328.8\u00d7. By combining minimal area, zero timing penalty, single-cycle correction latency, and guaranteed prevention of error accumulation, I-COR provides an efficient architectural-level fault-tolerance solution specifically designed for register file protection in safety-critical three-stage pipeline RISC-V processors.\n                  <\/jats:p>","DOI":"10.1145\/3787103","type":"journal-article","created":{"date-parts":[[2026,1,2]],"date-time":"2026-01-02T21:04:12Z","timestamp":1767387852000},"page":"1-25","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["I-COR: Instruction-Level Fault Tolerance for Register File in 3-Stage Pipeline RISC-V Processors"],"prefix":"10.1145","volume":"25","author":[{"ORCID":"https:\/\/orcid.org\/0009-0003-2951-2130","authenticated-orcid":false,"given":"Zewen","family":"Cao","sequence":"first","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences","place":["Beijing, China"]},{"name":"University of Chinese Academy of Sciences","place":["Beijing, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0008-2416-6511","authenticated-orcid":false,"given":"Ying","family":"Yang","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences","place":["Beijing, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0002-2259-6063","authenticated-orcid":false,"given":"Qi","family":"Wang","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences","place":["Beijing, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2026,3,3]]},"reference":[{"key":"e_1_3_1_2_2","doi-asserted-by":"publisher","unstructured":"Aurelien Alacchi Edouard Giacomin Scott Temple Roman Gauchi Michael Wirthlin and Pierre-Emmanuel Gaillardon. 2023. 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