{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,18]],"date-time":"2026-06-18T14:53:33Z","timestamp":1781794413077,"version":"3.54.5"},"publisher-location":"New York, NY, USA","reference-count":38,"publisher":"ACM","license":[{"start":{"date-parts":[[2026,6,22]],"date-time":"2026-06-22T00:00:00Z","timestamp":1782086400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"}],"funder":[{"DOI":"10.13039\/100000001","name":"NSF (National Science Foundation)","doi-asserted-by":"publisher","award":["2618386"],"award-info":[{"award-number":["2618386"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"NSF (National Science Foundation)","doi-asserted-by":"publisher","award":["2611359"],"award-info":[{"award-number":["2611359"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"NSF (National Science Foundation)","doi-asserted-by":"publisher","award":["2611357"],"award-info":[{"award-number":["2611357"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"NSF (National Science Foundation)","doi-asserted-by":"publisher","award":["2611350"],"award-info":[{"award-number":["2611350"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"NSF (National Science Foundation)","doi-asserted-by":"publisher","award":["2611071"],"award-info":[{"award-number":["2611071"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"NSF (National Science Foundation)","doi-asserted-by":"publisher","award":["2610355"],"award-info":[{"award-number":["2610355"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"NSF (National Science Foundation)","doi-asserted-by":"publisher","award":["2510192"],"award-info":[{"award-number":["2510192"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"NSF (National Science Foundation)","doi-asserted-by":"publisher","award":["2408064"],"award-info":[{"award-number":["2408064"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000015","name":"DOE U.S. Department of Energy","doi-asserted-by":"publisher","award":["DE-SC0025561"],"award-info":[{"award-number":["DE-SC0025561"]}],"id":[{"id":"10.13039\/100000015","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2026,6,22]]},"DOI":"10.1145\/3787109.3815222","type":"proceedings-article","created":{"date-parts":[[2026,6,18]],"date-time":"2026-06-18T14:17:19Z","timestamp":1781792239000},"page":"171-178","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Reliability-Driven Sneak Path Current Modeling and Optimization for Passive Memristor Crossbar Arrays"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-0926-2838","authenticated-orcid":false,"given":"Zhenlin","family":"Pei","sequence":"first","affiliation":[{"name":"The University of Alabama, Tuscaloosa, AL, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4236-5465","authenticated-orcid":false,"given":"Shah Zayed","family":"Riam","sequence":"additional","affiliation":[{"name":"The University of Alabama, Tuscaloosa, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0001-4439-6268","authenticated-orcid":false,"given":"Kyle","family":"Mooney","sequence":"additional","affiliation":[{"name":"The University of Alabama, Tuscaloosa, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9161-1728","authenticated-orcid":false,"given":"Chenyun","family":"Pan","sequence":"additional","affiliation":[{"name":"The University of Texas at Arlington, Arlington, TX, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3297-7436","authenticated-orcid":false,"given":"Na","family":"Gong","sequence":"additional","affiliation":[{"name":"The University of Alabama, Tuscaloosa, AL, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4731-8481","authenticated-orcid":false,"given":"Jinhui","family":"Wang","sequence":"additional","affiliation":[{"name":"The University of Alabama, Tuscaloosa, AL, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2026,6,22]]},"reference":[{"key":"e_1_3_3_1_1_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCT.1971.1083337"},{"key":"e_1_3_3_1_2_2","first-page":"5","volume-title":"Sizing-priority based low-power embedded memory for mobile video applications,\" in 2016 17th International Symposium on Quality Electronic Design (ISQED)","author":"Pourbakhsh S. A.","year":"2016","unstructured":"S. A. Pourbakhsh, X. Chen, D. Chen, X. Wang, N. Gong, and J. Wang, \"Sizing-priority based low-power embedded memory for mobile video applications,\" in 2016 17th International Symposium on Quality Electronic Design (ISQED), 2016: IEEE, pp. 1\u20135."},{"key":"e_1_3_3_1_3_2","doi-asserted-by":"publisher","DOI":"10.1049\/el.2012.0039"},{"key":"e_1_3_3_1_4_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.mee.2016.03.014"},{"key":"e_1_3_3_1_5_2","first-page":"101","article-title":"Memristive crossbar-based nonvolatile memory","author":"Vourkas I.","year":"2015","unstructured":"I. Vourkas and G. C. Sirakoulis, \"Memristive crossbar-based nonvolatile memory,\" in Memristor-Based Nanoelectronic Computing Circuits and Architectures: Springer, 2015, pp. 101\u2013147.","journal-title":"Memristor-Based Nanoelectronic Computing Circuits and Architectures: Springer"},{"key":"e_1_3_3_1_6_2","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2011.2165690"},{"key":"e_1_3_3_1_7_2","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2019.2908997"},{"key":"e_1_3_3_1_8_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2014.2298280"},{"key":"e_1_3_3_1_9_2","doi-asserted-by":"publisher","DOI":"10.1021\/nl203687n"},{"key":"e_1_3_3_1_10_2","doi-asserted-by":"publisher","DOI":"10.1021\/nl8037689"},{"key":"e_1_3_3_1_11_2","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-018-0115-z"},{"key":"e_1_3_3_1_12_2","first-page":"245","article-title":"Carbon efficiency of natural organic honey-memristor based neuromorphic computing","volume":"2025","author":"Uppaluru H.","year":"2025","unstructured":"H. Uppaluru, Z. Templin, S. Z. Riam, F. Zhao, and J. Wang, \"Carbon efficiency of natural organic honey-memristor based neuromorphic computing,\" in Proceedings of the Great Lakes Symposium on VLSI 2025, 2025, pp. 245\u2013251.","journal-title":"Proceedings of the Great Lakes Symposium on VLSI"},{"key":"e_1_3_3_1_13_2","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2022.3207687"},{"key":"e_1_3_3_1_14_2","first-page":"585","volume-title":"Reliability improvement in rram-based dnn for edge computing,\" in 2022 IEEE international symposium on circuits and systems (ISCAS)","author":"Oli-Uz-Zaman M.","year":"2022","unstructured":"M. Oli-Uz-Zaman, S. A. Khan, G. Yuan, Y. Wang, Z. Liao, J. Fu, C. Ding, and J. Wang, \"Reliability improvement in rram-based dnn for edge computing,\" in 2022 IEEE international symposium on circuits and systems (ISCAS), 2022: IEEE, pp. 581\u2013585."},{"key":"e_1_3_3_1_15_2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-031-02030-8"},{"key":"e_1_3_3_1_16_2","first-page":"160","volume-title":"Sneak-path constraints in memristor crossbar arrays,\" in 2013 IEEE international symposium on information theory","author":"Cassuto Y.","year":"2013","unstructured":"Y. Cassuto, S. Kvatinsky, and E. Yaakobi, \"Sneak-path constraints in memristor crossbar arrays,\" in 2013 IEEE international symposium on information theory, 2013: IEEE, pp. 156\u2013160."},{"key":"e_1_3_3_1_17_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.rinp.2018.12.092"},{"key":"e_1_3_3_1_18_2","doi-asserted-by":"publisher","DOI":"10.3390\/electronics7100224"},{"key":"e_1_3_3_1_19_2","first-page":"3","volume-title":"IEEE","author":"Liang J.","unstructured":"J. Liang and H.-S. P. Wong, \"Size limitation of cross-point memory array and its dependence on data storage pattern and device parameters,\" in 2010 IEEE International Interconnect Technology Conference, 2010: IEEE, pp. 1\u20133."},{"key":"e_1_3_3_1_20_2","volume-title":"Linear optimization for memristive device in neuromorphic hardware,\" in 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","author":"Fu J.","year":"2019","unstructured":"J. Fu, Z. Liao, N. Gong, and J. Wang, \"Linear optimization for memristive device in neuromorphic hardware,\" in 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2019."},{"key":"e_1_3_3_1_21_2","doi-asserted-by":"publisher","DOI":"10.1080\/00207217.2020.1843716"},{"key":"e_1_3_3_1_22_2","doi-asserted-by":"publisher","DOI":"10.1088\/0957-4484\/20\/42\/425204"},{"key":"e_1_3_3_1_23_2","doi-asserted-by":"publisher","DOI":"10.1007\/s10825-020-01470-0"},{"key":"e_1_3_3_1_24_2","first-page":"292","volume-title":"Design considerations for variation tolerant multilevel CMOS\/Nano memristor memory,\" in Proceedings of the 20th symposium on Great lakes symposium on VLSI","author":"Manem H.","year":"2010","unstructured":"H. Manem, G. S. Rose, X. He, and W. Wang, \"Design considerations for variation tolerant multilevel CMOS\/Nano memristor memory,\" in Proceedings of the 20th symposium on Great lakes symposium on VLSI, 2010, pp. 287\u2013292."},{"key":"e_1_3_3_1_25_2","doi-asserted-by":"publisher","DOI":"10.1038\/nmat2748"},{"key":"e_1_3_3_1_26_2","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2013.2246791"},{"key":"e_1_3_3_1_27_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2012.10.001"},{"key":"e_1_3_3_1_28_2","doi-asserted-by":"publisher","DOI":"10.1039\/D0NA00100G"},{"key":"e_1_3_3_1_29_2","first-page":"391","volume-title":"Sneak-path testing of memristor-based memories,\" in 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems","author":"Kannan S.","year":"2013","unstructured":"S. Kannan, J. Rajendran, R. Karri, and O. Sinanoglu, \"Sneak-path testing of memristor-based memories,\" in 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems, 2013: IEEE, pp. 386\u2013391."},{"key":"e_1_3_3_1_30_2","first-page":"23","volume-title":"CiMLoop: A flexible, accurate, and fast compute-in-memory modeling tool,\" in 2024 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)","author":"Andrulis T.","year":"2024","unstructured":"T. Andrulis, J. S. Emer, and V. Sze, \"CiMLoop: A flexible, accurate, and fast compute-in-memory modeling tool,\" in 2024 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2024: IEEE, pp. 10\u201323."},{"key":"e_1_3_3_1_31_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2023.3251696"},{"key":"e_1_3_3_1_32_2","first-page":"7","volume-title":"MLP+ NeuroSimV3. 0: Improving on-chip learning performance with device to algorithm optimizations,\" in Proceedings of the international conference on neuromorphic systems","author":"Luo Y.","year":"2019","unstructured":"Y. Luo, X. Peng, and S. Yu, \"MLP+ NeuroSimV3. 0: Improving on-chip learning performance with device to algorithm optimizations,\" in Proceedings of the international conference on neuromorphic systems, 2019, pp. 1\u20137."},{"key":"e_1_3_3_1_33_2","volume-title":"A deep neural network deployment based on resistive memory accelerator simulation,\" arXiv preprint arXiv:2304.11337","author":"Maram T. R.","year":"2023","unstructured":"T. R. Maram and R. Barnwal, \"A deep neural network deployment based on resistive memory accelerator simulation,\" arXiv preprint arXiv:2304.11337, 2023."},{"key":"e_1_3_3_1_34_2","doi-asserted-by":"publisher","DOI":"10.1038\/s41586-023-05759-5"},{"key":"e_1_3_3_1_35_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.sse.2008.09.018"},{"key":"e_1_3_3_1_36_2","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2025.3540760"},{"key":"e_1_3_3_1_37_2","volume-title":"Ngspice: Open Source Spice Simulator. https:\/\/ngspice.sourceforge.io\/.\u00a0","author":"Team The Ngspice","year":"2026","unstructured":"The Ngspice Team. Ngspice: Open Source Spice Simulator. https:\/\/ngspice.sourceforge.io\/.\u00a0 2026."},{"key":"e_1_3_3_1_38_2","first-page":"800","volume-title":"Unlocking sneak path analysis in memristor based logic design styles,\" in 2022 25th Euromicro Conference on Digital System Design (DSD)","author":"Datta K.","year":"2022","unstructured":"K. Datta, S. Shirinzadeh, P. L. Thangkhiew, I. Sengupta, and R. Drechsler, \"Unlocking sneak path analysis in memristor based logic design styles,\" in 2022 25th Euromicro Conference on Digital System Design (DSD), 2022: IEEE, pp. 793\u2013800."}],"event":{"name":"GLSVLSI '26: Great Lakes Symposium on VLSI 2026","location":"Canandaigua , NY , USA","acronym":"GLSVLSI '26","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CEDA"]},"container-title":["Proceedings of the Great Lakes Symposium on VLSI 2026"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/abs\/10.1145\/3787109.3815222","content-type":"text\/html","content-version":"vor","intended-application":"syndication"}],"deposited":{"date-parts":[[2026,6,18]],"date-time":"2026-06-18T14:17:56Z","timestamp":1781792276000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3787109.3815222"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,6,22]]},"references-count":38,"alternative-id":["10.1145\/3787109.3815222","10.1145\/3787109"],"URL":"https:\/\/doi.org\/10.1145\/3787109.3815222","relation":{},"subject":[],"published":{"date-parts":[[2026,6,22]]},"assertion":[{"value":"2026-06-22","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}