{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,18]],"date-time":"2026-06-18T14:53:38Z","timestamp":1781794418719,"version":"3.54.5"},"publisher-location":"New York, NY, USA","reference-count":15,"publisher":"ACM","license":[{"start":{"date-parts":[[2026,6,22]],"date-time":"2026-06-22T00:00:00Z","timestamp":1782086400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2026,6,22]]},"DOI":"10.1145\/3787109.3815235","type":"proceedings-article","created":{"date-parts":[[2026,6,18]],"date-time":"2026-06-18T14:17:19Z","timestamp":1781792239000},"page":"392-397","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["BitPair: An Efficient 2-Bit Serial Precision-Scalable Accelerator for GEMM in Deep Neural Networks"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0009-0009-9498-0428","authenticated-orcid":false,"given":"Jinhua","family":"Li","sequence":"first","affiliation":[{"name":"State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, Shanghai, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0001-9796-6471","authenticated-orcid":false,"given":"Menghan","family":"Li","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, Shanghai, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8742-687X","authenticated-orcid":false,"given":"Jun","family":"Tao","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, Shanghai, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5245-0754","authenticated-orcid":false,"given":"Jun","family":"Han","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, Shanghai, China"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2026,6,22]]},"reference":[{"key":"e_1_3_3_1_2_2","doi-asserted-by":"publisher","unstructured":"Ahmed\u00a0J. Abdelmaksoud Shady Agwa and Themis Prodromakis. 2026. DiP: A Scalable Energy-Efficient Systolic Array for Matrix Multiplication Acceleration. IEEE Transactions on Circuits and Systems I: Regular Papers 73 1 (2026) 283\u2013293. 10.1109\/TCSI.2025.3591960","DOI":"10.1109\/TCSI.2025.3591960"},{"key":"e_1_3_3_1_3_2","doi-asserted-by":"publisher","unstructured":"Saraswathy B. and Anita\u00a0Angeline A.2025. Dynamic precision configurable multiply and accumulate architecture for hardware accelerators. Integr. VLSI J. 103 C (July 2025) 8\u00a0pages. 10.1016\/j.vlsi.2025.102419","DOI":"10.1016\/j.vlsi.2025.102419"},{"key":"e_1_3_3_1_4_2","doi-asserted-by":"publisher","DOI":"10.1109\/CVPRW50498.2020.00356"},{"key":"e_1_3_3_1_5_2","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP61560.2024.00020"},{"key":"e_1_3_3_1_6_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783722"},{"key":"e_1_3_3_1_7_2","unstructured":"Jung\u00a0Hyun Lee Seungjae Shin Vinnam Kim Jaeseong You and An Chen. 2025. Unifying Block-wise PTQ and Distillation-based QAT for Progressive Quantization toward 2-bit Instruction-Tuned LLMs. arXiv preprint arXiv:https:\/\/arXiv.org\/abs\/2506.09104 (2025)."},{"key":"e_1_3_3_1_8_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCV51070.2023.01580"},{"key":"e_1_3_3_1_9_2","unstructured":"Kai Liu Qian Zheng Kaiwen Tao Zhiteng Li Haotong Qin Wenbo Li Yong Guo Xianglong Liu Linghe Kong Guihai Chen et\u00a0al. 2025. Low-bit model quantization for deep neural networks: A survey. arXiv preprint arXiv:https:\/\/arXiv.org\/abs\/2505.05530 (2025)."},{"key":"e_1_3_3_1_10_2","unstructured":"Markus Nagel Marios Fournarakis Rana\u00a0Ali Amjad Yelysei Bondarenko Mart Van\u00a0Baalen and Tijmen Blankevoort. 2021. A white paper on neural network quantization. arXiv preprint arXiv:https:\/\/arXiv.org\/abs\/2106.08295 (2021)."},{"key":"e_1_3_3_1_11_2","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317784"},{"key":"e_1_3_3_1_12_2","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2018.8465915"},{"key":"e_1_3_3_1_13_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00069"},{"key":"e_1_3_3_1_14_2","doi-asserted-by":"publisher","DOI":"10.1145\/3503161.3548001"},{"key":"e_1_3_3_1_15_2","unstructured":"Hao Wu Patrick Judd Xiaojie Zhang Mikhail Isaev and Paulius Micikevicius. 2020. Integer quantization for deep learning inference: Principles and empirical evaluation. arXiv preprint arXiv:https:\/\/arXiv.org\/abs\/2004.09602 (2020)."},{"key":"e_1_3_3_1_16_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA61900.2025.00058"}],"event":{"name":"GLSVLSI '26: Great Lakes Symposium on VLSI 2026","location":"Canandaigua , NY , USA","acronym":"GLSVLSI '26","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CEDA"]},"container-title":["Proceedings of the Great Lakes Symposium on VLSI 2026"],"original-title":[],"deposited":{"date-parts":[[2026,6,18]],"date-time":"2026-06-18T14:18:27Z","timestamp":1781792307000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3787109.3815235"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,6,22]]},"references-count":15,"alternative-id":["10.1145\/3787109.3815235","10.1145\/3787109"],"URL":"https:\/\/doi.org\/10.1145\/3787109.3815235","relation":{},"subject":[],"published":{"date-parts":[[2026,6,22]]},"assertion":[{"value":"2026-06-22","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}