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Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2026,3,31]]},"abstract":"<jats:p>Control and Status Registers (CSRs) are fundamental to the RISC-V architecture, providing a versatile interface for managing processor state, system configuration, and functionality like exception handling, debugging, and performance monitoring. However, their implementation in FPGA-based systems poses challenges due to the inherent constraints of FPGA resources. The need for atomic parallel access to all CSRs, coupled with limitations of conventional LUT-based multiplexing, increases logic depth and resource usage\u2004, degrading Fmax in large-scale implementations. This work explores these obstacles and introduces optimized mechanisms to improve CSR handling efficiency. A minimal microarchitectural environment was built to isolate and evaluate multiple access strategies, retaining only components essential to CSR interaction. Leveraging a heterogeneous design tailored to FPGA \u2004capabilities\u2014featuring BRAM for decoding, DSPs for multiplexing, and LUTs, CARRYs and flip-flops to facilitate routing\u2014the proposed CSR subsystem achieves performance enhancements ranging from 50% to over 300%, contingent upon configuration. The top-performing implementation reaches 250\u2009MHz on Artix-7 FPGAs while simultaneously reducing area and dynamic power. These results challenge prevailing reliance on abstract electronic design, highlighting that hardware-aware low-level methodologies can yield superior quality-of-results (QoR) over pure behavioral descriptions. More broadly, the findings inform datapath optimization involving decoding and multiplexing in performance-critical and resource-constrained digital architectures.<\/jats:p>","DOI":"10.1145\/3787491","type":"journal-article","created":{"date-parts":[[2026,1,19]],"date-time":"2026-01-19T14:06:03Z","timestamp":1768831563000},"page":"1-34","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["High-Performance RISC-V CSR Access in FPGAs: Optimized Microarchitecture for Efficient Decoding and Multiplexing"],"prefix":"10.1145","volume":"19","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-6209-9742","authenticated-orcid":false,"given":"Miguel","family":"Jim\u00e9nez Arribas","sequence":"first","affiliation":[{"name":"Autom\u00e1tica, University of Alcal\u00e1, Alcal\u00e1 de Henares, Spain"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5600-9253","authenticated-orcid":false,"given":"Agust\u00edn","family":"Mart\u00ednez Hell\u00edn","sequence":"additional","affiliation":[{"name":"Autom\u00e1tica, University of Alcal\u00e1, Alcal\u00e1 de Henares, Spain"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3050-3445","authenticated-orcid":false,"given":"Manuel","family":"Prieto Mateo","sequence":"additional","affiliation":[{"name":"Autom\u00e1tica, University of Alcal\u00e1, Alcal\u00e1 de Henares, Spain"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2026,3,6]]},"reference":[{"key":"e_1_3_2_2_2","doi-asserted-by":"publisher","DOI":"10.1145\/3686081.3686117"},{"key":"e_1_3_2_3_2","unstructured":"Pablo Valerio. 2025. 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