{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,10]],"date-time":"2026-02-10T20:03:52Z","timestamp":1770753832180,"version":"3.50.0"},"reference-count":55,"publisher":"Association for Computing Machinery (ACM)","issue":"3","funder":[{"name":"Spoke 1 \u201cFutureHPC & BigData\u201d"},{"name":"Spoke 9 \u201cDigital Society & Smart Cities\u201d"},{"name":"European Union - NextGenerationEU"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2026,5,31]]},"abstract":"<jats:p>\n                    The recent rise of open hardware, mainly driven by the momentum of the RISC-V ecosystem, has sparked significant innovation in the development of open-source CPUs and SoCs. This movement has enabled broad exploration across academia and industry, fostering collaboration and reuse. However, the diversity and openness that empower this space also introduce challenges: academic projects often fall short of industry-grade robustness, and meaningful comparison across hardware platforms remains difficult due to ad hoc infrastructures, lack of standardization, and simulation limitations. To ease the work of researchers some key challenges must be faced in open hardware development: platforms\u2019 reconfigurability, ease of integration of third-party IPs, and support for technological heterogeneity. A core problem lies in validating and comparing CPUs and SoC components across varying protocols, toolchains, and design languages, especially in real hardware settings. To address these issues, we present Simply-V, a flexible FPGA-based soft-SoC platform designed for rapid prototyping and open hardware research. Simply-V enables plug-and-play support for multiple CPUs, IPs and accelerators, offers structured configurability across embedded and high-performance profiles, and supports the integration of both RTL and HLS-based components. Capabilities such as a high-level configuration flow, frequency scaling, and cross-device portability make our platform a powerful tool to simplify open hardware research. We demonstrate the SoC generator\u2019s capabilities through multi-task FreeRTOS examples, platform-fair CPU benchmarking and the iterative development of HLS-designed convolutional accelerators. Moreover, we validate multi-accelerator and multi-CPU scalability and compare with the state-of-the-art SoC generators. Our platform showcases simplified fast prototyping, configurability, scalability and heterogeneous IP support on real hardware. Simply-V is openly available at\n                    <jats:ext-link xmlns:xlink=\"http:\/\/www.w3.org\/1999\/xlink\" xlink:href=\"https:\/\/github.com\/HiSA-Team\/Simply-V\">https:\/\/github.com\/HiSA-Team\/Simply-V<\/jats:ext-link>\n                    .\n                  <\/jats:p>","DOI":"10.1145\/3787500","type":"journal-article","created":{"date-parts":[[2026,1,5]],"date-time":"2026-01-05T21:16:23Z","timestamp":1767647783000},"page":"1-32","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["The Simply-V Framework: An Extensible RISC-V Reconfigurable Soft-SoC for Open Research and Fast Prototyping"],"prefix":"10.1145","volume":"31","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-1631-1597","authenticated-orcid":false,"given":"Vincenzo","family":"Maisto","sequence":"first","affiliation":[{"name":"Department of Information Technoilogy and Electrical Engineering, University of Naples Federico II","place":["Naples, Italy"]}]},{"ORCID":"https:\/\/orcid.org\/0009-0000-3259-6820","authenticated-orcid":false,"given":"Stefano","family":"Mercogliano","sequence":"additional","affiliation":[{"name":"Department of Information Technoilogy and Electrical Engineering, University of Naples Federico II","place":["Naples, Italy"]}]},{"ORCID":"https:\/\/orcid.org\/0009-0001-2816-0095","authenticated-orcid":false,"given":"Manuel","family":"Maddaluno","sequence":"additional","affiliation":[{"name":"Department of Information Technoilogy and Electrical Engineering, University of Naples Federico II","place":["Naples, Italy"]}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1685-8736","authenticated-orcid":false,"given":"Alessandro","family":"Cilardo","sequence":"additional","affiliation":[{"name":"Department of Information Technoilogy and Electrical Engineering, University of Naples Federico II","place":["Naples, Italy"]}]}],"member":"320","published-online":{"date-parts":[[2026,2,10]]},"reference":[{"key":"e_1_3_1_2_2","volume-title":"Alveo Data Center Accelerator Card Platforms User Guide (UG1120)","author":"Xilinx AMD","year":"2025","unstructured":"AMD Xilinx. 2025. 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