{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,10,23]],"date-time":"2026-10-23T20:31:06Z","timestamp":1792787466494,"version":"4.5.0"},"reference-count":231,"publisher":"Association for Computing Machinery (ACM)","issue":"5","funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"crossref","award":["92373205, 92373206, 62222411, and 62025404"],"award-info":[{"award-number":["92373205, 92373206, 62222411, and 62025404"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"crossref"}]},{"name":"National Key Research and Development Program of China","award":["2023YFB4404400"],"award-info":[{"award-number":["2023YFB4404400"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2026,9,30]]},"abstract":"<jats:p>\n                    With the slowdown of Moore\u2019s Law, conventional monolithic chip architectures face challenges such as excessive die sizes and prohibitive manufacturing costs. Consequently, chiplets have emerged as a pivotal technology in the post-Moore era, attracting significant attention from both academia and industry. Multi-chiplet systems offer compelling advantages over monolithic ones, including enhanced integration density, reduced cost, and shortened time-to-market. However, realizing these benefits necessitates design flows capable of optimizing parameters across logical, physical, and circuit layers, which introduces substantial design complexity. Numerous design automation technologies have been proposed to address these challenges. This article provides a comprehensive overview of related advancements, categorizing chiplet design methodologies into two primary types: (i)\n                    <jats:bold>top-down<\/jats:bold>\n                    flows disintegrating existing hardware designs into chiplets and subsequently reintegrating them into multi-chiplet systems, and (ii)\n                    <jats:bold>bottom-up<\/jats:bold>\n                    flows combining existing chiplets into multi-chiplet systems based on user applications. This article begins by introducing foundational concepts, technical characteristics, and evaluation models relevant to multi-chiplet systems. We then systematically summarize the problem formulations, design spaces, and optimization techniques associated with top-down and bottom-up design flows. Finally, we discuss key challenges and potential future research directions in chiplet design automation, aimed at further harnessing the potential of chiplet-based integration.\n                  <\/jats:p>","DOI":"10.1145\/3796529","type":"journal-article","created":{"date-parts":[[2026,2,11]],"date-time":"2026-02-11T21:15:01Z","timestamp":1770844501000},"page":"1-56","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["Chiplet Design Automation: Methodologies, Advances, and Directions"],"prefix":"10.1145","volume":"31","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-7134-4981","authenticated-orcid":false,"given":"Fuping","family":"Li","sequence":"first","affiliation":[{"name":"SKLP, Institute of Computing Technology, CAS","place":["Beijing, China"]},{"name":"University of Chinese Academy of Sciences","place":["Beijing, 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