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Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2026,9,30]]},"abstract":"<jats:p>3D NAND flash memory is currently the mainstream storage medium due to high density and large capacity. However, the high raw bit error rate (RBER) poses challenges to data reliability. Low-density parity-check (LDPC) codes, known for strong error correction capabilities, are widely used to ensure data reliability. Traditional error correction schemes employ a single, fixed LDPC code, resulting in suboptimal performance\u2013excess decoding overhead at low RBER and insufficient correction capability at high RBER.<\/jats:p>\n                  <jats:p>To address these limitations, we propose DyLDPC: a dynamic LDPC code with variable correction capability to improve decoding performance for 3D NAND flash memory. DyLDPC dynamically adjusts the error correction capability of LDPC codes based on the temporal and spatial variations of RBER in 3D NAND flash memory. Temporally, RBER increases with retention time and program\/erase (P\/E) cycles. Spatially, RBER varies across layers and pages. DyLDPC predicts RBER under varying conditions and allocates appropriate LDPC codes accordingly, effectively reducing ECC storage overhead, extending flash memory lifespan, and improving decoding efficiency. While ensuring data reliability, it optimizes error correction performance. Evaluations indicate that DyLDPC reduces decoding iterations by 8.1% and latency by 74% on average compared to static schemes. Additionally, using differentiated LDPC codes for most significant bit (MSB) and least significant bit (LSB) pages in multi-level cell (MLC) NAND further reduces LSB decoding latency by 27.8%.<\/jats:p>","DOI":"10.1145\/3796534","type":"journal-article","created":{"date-parts":[[2026,2,9]],"date-time":"2026-02-09T21:09:38Z","timestamp":1770671378000},"page":"1-25","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["DyLDPC: A Dynamic LDPC Code with Variable Correction Capability to Improve Decoding Performance for 3D NAND Flash Memory"],"prefix":"10.1145","volume":"31","author":[{"ORCID":"https:\/\/orcid.org\/0009-0007-0020-1661","authenticated-orcid":false,"given":"Geyang","family":"Ren","sequence":"first","affiliation":[{"name":"Huazhong University of Science and Technology","place":["Wuhan, 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