{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,27]],"date-time":"2026-04-27T15:03:02Z","timestamp":1777302182374,"version":"3.51.4"},"reference-count":37,"publisher":"Association for Computing Machinery (ACM)","issue":"2","funder":[{"name":"Science Foundation of Guangdong Province","award":["2025A1515010110"],"award-info":[{"award-number":["2025A1515010110"]}]},{"name":"Basic and Applied Fundamental Research Topics of Guangzhou","award":["2025A04J3753"],"award-info":[{"award-number":["2025A04J3753"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2026,4,30]]},"abstract":"<jats:p>The SystemC language, with its higher level of abstraction, plays a critical role in facilitating hardware\/software co-design and architecture exploration. However, as most hardware models are predominantly written in Verilog and translating between SystemC and Verilog remains a challenge, an efficient and reliable tool for translating between these two languages is essential to streamline system development. This article proposes SCAV, a bidirectional translator between SystemC and Verilog, which breaks these limitations. SCAV provides a fully automated solution for translating both SystemC to Verilog and Verilog to SystemC, leveraging a translation framework with front-end\/back-end separation. Additionally, SCAV incorporates an Abstract Syntax Tree (AST) filter, optimizing the translation process by filtering out invalid content. The experimental results demonstrate that SCAV achieves a 100% adaptation rate for Verilog and a 98% adaptation rate for SystemC, with 100% accuracy in both directions. Furthermore, SCAV outperforms existing tools, delivering a minimum speedup of 18% across various test cases.<\/jats:p>","DOI":"10.1145\/3798042","type":"journal-article","created":{"date-parts":[[2026,2,28]],"date-time":"2026-02-28T08:54:16Z","timestamp":1772268856000},"page":"1-19","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["High-Efficiency Bidirectional Translator between SystemC and Verilog"],"prefix":"10.1145","volume":"22","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-4931-9664","authenticated-orcid":false,"given":"Xin","family":"Zheng","sequence":"first","affiliation":[{"name":"School of Integrated Circuits, Guangdong University of Technology, Guangzhou, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0001-2575-6803","authenticated-orcid":false,"given":"Yongfeng","family":"Zhong","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Guangdong University of Technology, Guangzhou, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0000-7376-4819","authenticated-orcid":false,"given":"Chenyu","family":"Huang","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Guangdong University of Technology, Guangzhou, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0004-1860-4854","authenticated-orcid":false,"given":"Shaofen","family":"Zeng","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Guangdong University of Technology, Guangzhou, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0001-0528-3076","authenticated-orcid":false,"given":"Huaien","family":"Gao","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Guangdong University of Technology, Guangzhou, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2842-6439","authenticated-orcid":false,"given":"Shuting","family":"Cai","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Guangdong University of Technology, Guangzhou, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2421-7621","authenticated-orcid":false,"given":"Xiaoming","family":"Xiong","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Guangdong University of Technology, Guangzhou, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2026,4,27]]},"reference":[{"key":"e_1_3_2_2_2","first-page":"39","article-title":"Research on system-level verification platform for SOC","volume":"27","author":"Guo Tao Zuo Fengguo Luo Jun","year":"2018","unstructured":"Zuo Fengguo Luo Jun Guo Tao, Zhang Xiuqin, and Zhang Xiaochen. 2018. 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