{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,27]],"date-time":"2026-06-27T07:47:12Z","timestamp":1782546432967,"version":"3.54.5"},"publisher-location":"New York, NY, USA","reference-count":23,"publisher":"ACM","license":[{"start":{"date-parts":[[2026,5,19]],"date-time":"2026-05-19T00:00:00Z","timestamp":1779148800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"}],"funder":[{"name":"french ANR","award":["ANR-23-PEIA-0010"],"award-info":[{"award-number":["ANR-23-PEIA-0010"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2026,5,19]]},"DOI":"10.1145\/3801487.3801837","type":"proceedings-article","created":{"date-parts":[[2026,6,27]],"date-time":"2026-06-27T07:05:47Z","timestamp":1782543947000},"page":"169-178","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Network Folding for Resource-Efficient Implementation of Stream-Dataflow Deep Neural Network Inference on FPGAs"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0009-0003-8795-1780","authenticated-orcid":false,"given":"Van-Quan","family":"Pham","sequence":"first","affiliation":[{"name":"Univ. Grenoble Alpes, CNRS, Inria, Grenoble INP, TIMA, Grenoble, France"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2444-1412","authenticated-orcid":false,"given":"Adrien","family":"Prost-Boucle","sequence":"additional","affiliation":[{"name":"Univ. Grenoble Alpes, CNRS, Inria, Grenoble INP, TIMA, Grenoble, France"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4182-0502","authenticated-orcid":false,"given":"Olivier","family":"Muller","sequence":"additional","affiliation":[{"name":"Univ. Grenoble Alpes, CNRS, Inria, Grenoble INP, TIMA, Grenoble, France"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0624-7373","authenticated-orcid":false,"given":"Fr\u00e9d\u00e9ric","family":"P\u00e9trot","sequence":"additional","affiliation":[{"name":"Univ. Grenoble Alpes, CNRS, Inria, Grenoble INP, TIMA, Grenoble, France"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2026,6,27]]},"reference":[{"key":"e_1_3_3_2_2_2","doi-asserted-by":"publisher","DOI":"10.1109\/CVPRW53098.2021.00345"},{"key":"e_1_3_3_2_3_2","doi-asserted-by":"crossref","unstructured":"Tianshi Chen Zidong Du Ninghui Sun Jia Wang Chengyong Wu Yunji Chen and Olivier Temam. 2014. Diannao: A small-footprint high-throughput accelerator for ubiquitous machine-learning. ACM SIGARCH Computer Architecture News 42 1 (2014) 269\u2013284.","DOI":"10.1145\/2654822.2541967"},{"key":"e_1_3_3_2_4_2","doi-asserted-by":"publisher","DOI":"10.1109\/FPL64840.2024.00019"},{"key":"e_1_3_3_2_5_2","unstructured":"Epoch AI. 2025. Data on AI Models. https:\/\/epoch.ai\/data\/ai-models Accessed: 2025-08-29."},{"key":"e_1_3_3_2_6_2","first-page":"503","volume-title":"2024 27th Euromicro Conference on Digital System Design (DSD)","author":"al. Chen et","year":"2024","unstructured":"Chen et al.2024. High throughput and low bandwidth demand: Accelerating CNN inference block-by-block on FPGAs. In 2024 27th Euromicro Conference on Digital System Design (DSD). IEEE, 503\u2013511."},{"key":"e_1_3_3_2_7_2","unstructured":"Farah Fahim Benjamin Hawks et\u00a0al. 2021. hls4ml: An open-source codesign workflow to empower scientific low-power machine learning devices. arXiv preprint arXiv:https:\/\/arXiv.org\/abs\/2103.05579 (2021)."},{"key":"e_1_3_3_2_8_2","doi-asserted-by":"crossref","unstructured":"Mathew Hall and Vaughn Betz. 2020. HPIPE: Heterogeneous layer-pipelined and sparse-aware CNN inference for FPGAs. arXiv preprint arXiv:https:\/\/arXiv.org\/abs\/2007.10451 (2020).","DOI":"10.1145\/3373087.3375380"},{"key":"e_1_3_3_2_9_2","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.90"},{"key":"e_1_3_3_2_10_2","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2017.243"},{"key":"e_1_3_3_2_11_2","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080246"},{"key":"e_1_3_3_2_12_2","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR52688.2022.01167"},{"key":"e_1_3_3_2_13_2","doi-asserted-by":"publisher","DOI":"10.23919\/FPL.2017.8056824"},{"key":"e_1_3_3_2_14_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICFPT51103.2020.00016"},{"key":"e_1_3_3_2_15_2","unstructured":"Adrien Prost-Boucle. 2024. NNawaQ - Neural Network Adequate hardWare Architectures for Quantization. https:\/\/gricad-gitlab.univ-grenoble-alpes.fr\/tima\/public\/nnawaq\/nnawaq.git. Accessed: 2025-09-08."},{"key":"e_1_3_3_2_16_2","doi-asserted-by":"publisher","unstructured":"Adrien Prost-Boucle Alban Bourge and Fr\u00e9d\u00e9ric P\u00e9trot. 2018. High-Efficiency Convolutional Ternary Neural Networks with Custom Adder Trees and Weight Compression. ACM Transactions on Reconfigurable Technology and Systems 11 3 (Sept. 2018) 1\u201324. 10.1145\/3270764","DOI":"10.1145\/3270764"},{"key":"e_1_3_3_2_17_2","doi-asserted-by":"publisher","DOI":"10.1145\/3490422.3502364"},{"key":"e_1_3_3_2_18_2","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2015.7298594"},{"key":"e_1_3_3_2_19_2","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021744"},{"key":"e_1_3_3_2_20_2","unstructured":"Ashish Vaswani Noam Shazeer Niki Parmar Jakob Uszkoreit Llion Jones Aidan\u00a0N Gomez \u0141ukasz Kaiser and Illia Polosukhin. 2017. Attention is all you need. Advances in neural information processing systems 30 (2017)."},{"key":"e_1_3_3_2_21_2","doi-asserted-by":"crossref","unstructured":"Stylianos Venieris et\u00a0al. 2021. unzipFPGA: Enhancing FPGA-based CNN engines with on-the-fly weights generation. arXiv preprint arXiv:https:\/\/arXiv.org\/abs\/2103.05600 (2021).","DOI":"10.1109\/FCCM51124.2021.00027"},{"key":"e_1_3_3_2_22_2","first-page":"40","volume-title":"2020 International Conference on Field-Programmable Technology (ICFPT)","author":"Venieris Stylianos","year":"2016","unstructured":"Stylianos Venieris and Christos-Savvas Bouganis. 2016. fpgaConvNet: A framework for mapping convolutional neural networks on FPGAs. In 2020 International Conference on Field-Programmable Technology (ICFPT). IEEE, 40\u201347."},{"key":"e_1_3_3_2_23_2","doi-asserted-by":"crossref","unstructured":"Stylianos\u00a0I Venieris and Christos-Savvas Bouganis. 2018. fpgaConvNet: Mapping regular and irregular convolutional neural networks on FPGAs. IEEE transactions on neural networks and learning systems 30 2 (2018) 326\u2013342.","DOI":"10.1109\/TNNLS.2018.2844093"},{"key":"e_1_3_3_2_24_2","doi-asserted-by":"publisher","DOI":"10.1109\/FPL64840.2024.00043"}],"event":{"name":"CF '26: Proceedings of the 23rd ACM International Conference on Computing Frontiers","location":"Catania Italy","acronym":"CF '26","sponsor":["SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing"]},"container-title":["Proceedings of the 23rd ACM International Conference on Computing Frontiers"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3801487.3801837","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,6,27]],"date-time":"2026-06-27T07:10:20Z","timestamp":1782544220000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3801487.3801837"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,5,19]]},"references-count":23,"alternative-id":["10.1145\/3801487.3801837","10.1145\/3801487"],"URL":"https:\/\/doi.org\/10.1145\/3801487.3801837","relation":{},"subject":[],"published":{"date-parts":[[2026,5,19]]},"assertion":[{"value":"2026-06-27","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}