{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,12]],"date-time":"2026-06-12T11:59:53Z","timestamp":1781265593329,"version":"3.54.1"},"reference-count":53,"publisher":"Association for Computing Machinery (ACM)","issue":"6","license":[{"start":{"date-parts":[[2026,6,12]],"date-time":"2026-06-12T00:00:00Z","timestamp":1781222400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"}],"funder":[{"name":"The Research Grants Council of Hong Kong SAR","award":["No.\u00a0CUHK14211824 and No.\u00a0CUHK14210723"],"award-info":[{"award-number":["No.\u00a0CUHK14211824 and No.\u00a0CUHK14210723"]}]},{"name":"CCESS \u2013 AI Chip Center for Emerging Smart Systems"},{"name":"InnoHK initiative of the Innovation and Technology Commission of the Hong Kong Special Administrative Region Government"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2026,11,30]]},"abstract":"<jats:p>\n                    The rapid growth of deep neural network (DNN) applications has brought unprecedented challenges to the functionality and scalability of accelerators. To address these challenges, the multi-chip-module (MCM) approach facilitates the efficient and cost-effective development of accelerator architectures that can scale from mobile devices to data centers. Chiplet-based systems necessitate a robust platform capable of supporting both hardware modeling and software evaluation, since the performance of the entire system is not only determined by the design of functional units and interconnects, but also strongly affected by the scheduling and mapping of the dataflow. In this article, we propose Accelet, a comprehensive framework designed to articulate the hardware architecture of chiplet-based accelerators, as well as to investigate the scheduling and mapping strategies for DNN dataflows. Accelet\u2019s versatility in hardware and software modeling empowers the co-design of critical components, including functional units, interconnect topologies, system architectures, and mapping algorithms. Consequently, Accelet can stand as a pivotal tool for the hardware-software co-design of chiplet-based DNN accelerators. Accelet is available at\n                    <jats:monospace>\n                      <jats:ext-link xmlns:xlink=\"http:\/\/www.w3.org\/1999\/xlink\" xlink:href=\"https:\/\/github.com\/shelljane\/accelet-modeling\">https:\/\/github.com\/shelljane\/accelet-modeling<\/jats:ext-link>\n                    <\/jats:monospace>\n                    .\n                  <\/jats:p>","DOI":"10.1145\/3802577","type":"journal-article","created":{"date-parts":[[2026,3,26]],"date-time":"2026-03-26T20:56:45Z","timestamp":1774558605000},"page":"1-26","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Accelet: Hardware-software Co-design of Chiplet-based DNN Accelerators"],"prefix":"10.1145","volume":"31","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1159-1611","authenticated-orcid":false,"given":"Su","family":"Zheng","sequence":"first","affiliation":[{"name":"Computer Science and Engineering, The Chinese University of Hong Kong","place":["Hong Kong, Hong Kong"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6406-4810","authenticated-orcid":false,"given":"Bei","family":"Yu","sequence":"additional","affiliation":[{"name":"CSE, The Chinese University of Hong Kong","place":["Hong Kong, Hong Kong"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8274-9688","authenticated-orcid":false,"given":"Martin","family":"Wong","sequence":"additional","affiliation":[{"name":"Hong Kong Baptist University","place":["Hong Kong, Hong Kong"]}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2026,6,12]]},"reference":[{"key":"e_1_3_1_2_2","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3240801"},{"key":"e_1_3_1_3_2","doi-asserted-by":"publisher","DOI":"10.1145\/3289602.3293904"},{"key":"e_1_3_1_4_2","doi-asserted-by":"publisher","DOI":"10.1145\/3373087.3375311"},{"key":"e_1_3_1_5_2","doi-asserted-by":"publisher","DOI":"10.1145\/3400302.3415609"},{"key":"e_1_3_1_6_2","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218684"},{"key":"e_1_3_1_7_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.58"},{"key":"e_1_3_1_8_2","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750389"},{"key":"e_1_3_1_9_2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2616357"},{"key":"e_1_3_1_10_2","unstructured":"Nvidia. 2017. Nvdla deep learning accelerator. Retrieved from http:\/\/nvdla.org (2017)."},{"key":"e_1_3_1_11_2","unstructured":"2021. Google Cloud TPUv4. Retrieved from https:\/\/cloud.google.com\/tpu\/ (2021)."},{"key":"e_1_3_1_12_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA51647.2021.00016"},{"key":"e_1_3_1_13_2","first-page":"130","volume-title":"IEEE International Solid-State Circuits Conference (ISSCC)","author":"Song Jinook","year":"2019","unstructured":"Jinook Song, Yunkyo Cho, Jun-Seok Park, Jun-Woo Jang, Sehwan Lee, Joon-Ho Song, Jae-Gon Lee, and Inyup Kang. 2019. An 11.5 TOPS\/W 1024-MAC butterfly structure dual-core sparsity-aware neural processing unit in 8nm flagship mobile SoC. In IEEE International Solid-State Circuits Conference (ISSCC). 130\u2013132."},{"key":"e_1_3_1_14_2","first-page":"134","volume-title":"IEEE International Solid-State Circuits Conference (ISSCC)","author":"Lin Chien-Hung","year":"2020","unstructured":"Chien-Hung Lin, Chih-Chung Cheng, Yi-Min Tsai, Sheng-Je Hung, Yu-Ting Kuo, Perry H. Wang, Pei-Kuei Tsung, Jeng-Yun Hsu, Wei-Chih Lai, Chia-Hung Liu, et\u00a0al. 2020. A 3.4-to-13.3 TOPS\/W 3.6 TOPS dual-core deep-learning accelerator for versatile AI applications in 7nm 5G smartphone SoC. In IEEE International Solid-State Circuits Conference (ISSCC). 134\u2013136."},{"key":"e_1_3_1_15_2","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18074.2021.9586216"},{"key":"e_1_3_1_16_2","doi-asserted-by":"publisher","DOI":"10.1145\/3460227"},{"key":"e_1_3_1_17_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA52012.2021.00083"},{"key":"e_1_3_1_18_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA57654.2024.00022"},{"key":"e_1_3_1_19_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2019.00042"},{"key":"e_1_3_1_20_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2024.3386067"},{"key":"e_1_3_1_21_2","doi-asserted-by":"publisher","DOI":"10.23919\/DATE54114.2022.9774568"},{"key":"e_1_3_1_22_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA53966.2022.00065"},{"key":"e_1_3_1_23_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.cosrev.2020.100267"},{"key":"e_1_3_1_24_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.dam.2018.02.018"},{"key":"e_1_3_1_25_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA47549.2020.00015"},{"key":"e_1_3_1_26_2","doi-asserted-by":"publisher","DOI":"10.1145\/3392717.3392751"},{"key":"e_1_3_1_27_2","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218710"},{"key":"e_1_3_1_28_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.55"},{"key":"e_1_3_1_29_2","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218657"},{"key":"e_1_3_1_30_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD45719.2019.8942149"},{"key":"e_1_3_1_31_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA52012.2021.00050"},{"key":"e_1_3_1_32_2","doi-asserted-by":"publisher","DOI":"10.1145\/3400302.3415639"},{"key":"e_1_3_1_33_2","doi-asserted-by":"publisher","DOI":"10.1145\/3445814.3446762"},{"key":"e_1_3_1_34_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2021.3059962"},{"key":"e_1_3_1_35_2","doi-asserted-by":"publisher","DOI":"10.1109\/TKDE.2016.2566618"},{"key":"e_1_3_1_36_2","unstructured":"Hewlett Packard. 2026. CACTI: A Tool to Model Caches\/Memories 3D stacking and off-chip IO. Retrieved from https:\/\/github.com\/HewlettPackard\/cacti\/ ([n. d.])."},{"key":"e_1_3_1_37_2","first-page":"276","volume-title":"IEEE International Solid-State Circuits Conference (ISSCC)","author":"Wilson John M.","year":"2018","unstructured":"John M. Wilson, Walker J. Turner, John W. Poulton, Brian Zimmer, Xi Chen, Sudhir S. Kudva, Sanquan Song, Stephen G. Tell, Nikola Nedovic, Wenxu Zhao, et\u00a0al. 2018. A 1.17 pJ\/b 25Gb\/s\/pin ground-referenced single-ended serial link for off-and on-package communication in 16nm CMOS using a process-and temperature-adaptive voltage regulator. In IEEE International Solid-State Circuits Conference (ISSCC). 276\u2013278."},{"key":"e_1_3_1_38_2","doi-asserted-by":"publisher","DOI":"10.1145\/2647868.2654889"},{"key":"e_1_3_1_39_2","unstructured":"Thomas N. Kipf and Max Welling. 2016. Semi-supervised classification with graph convolutional networks. arXiv:1609.02907. Retrieved from https:\/\/arxiv.org\/abs\/1609.02907"},{"key":"e_1_3_1_40_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCV51070.2023.00556"},{"key":"e_1_3_1_41_2","article-title":"Neural ordinary differential equations","volume":"31","author":"Chen Ricky T. Q.","year":"2018","unstructured":"Ricky T. Q. Chen, Yulia Rubanova, Jesse Bettencourt, and David K. Duvenaud. 2018. Neural ordinary differential equations. Annual Conference on Neural Information Processing Systems (NeurIPS) 31 (2018), 6572\u20136583.","journal-title":"Annual Conference on Neural Information Processing Systems (NeurIPS)"},{"key":"e_1_3_1_42_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD51958.2021.9643455"},{"key":"e_1_3_1_43_2","doi-asserted-by":"publisher","DOI":"10.1145\/3508352.3561109"},{"key":"e_1_3_1_44_2","doi-asserted-by":"publisher","DOI":"10.1145\/3597931"},{"key":"e_1_3_1_45_2","doi-asserted-by":"publisher","DOI":"10.1109\/ASP-DAC58780.2024.10473826"},{"key":"e_1_3_1_46_2","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218539"},{"key":"e_1_3_1_47_2","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.90"},{"key":"e_1_3_1_48_2","volume-title":"International Conference on Learning Representations (ICLR)","author":"Dosovitskiy Alexey","year":"2026","unstructured":"Alexey Dosovitskiy, Lucas Beyer, Alexander Kolesnikov, Dirk Weissenborn, Xiaohua Zhai, Thomas Unterthiner, Mostafa Dehghani, Matthias Minderer, Georg Heigold, Sylvain Gelly, et\u00a0al. 2026. An image is worth 16x16 Words: Transformers for image recognition at scale. In International Conference on Learning Representations (ICLR)."},{"key":"e_1_3_1_49_2","doi-asserted-by":"publisher","DOI":"10.1613\/jair.1.13188"},{"key":"e_1_3_1_50_2","doi-asserted-by":"publisher","DOI":"10.1109\/4235.996017"},{"key":"e_1_3_1_51_2","first-page":"6105","volume-title":"International Conference on Machine Learning (ICML)","author":"Tan Mingxing","year":"2019","unstructured":"Mingxing Tan and Quoc Le. 2019. Efficientnet: Rethinking model scaling for convolutional neural networks. In International Conference on Machine Learning (ICML). PMLR, 6105\u20136114."},{"key":"e_1_3_1_52_2","first-page":"4171","volume-title":"Annual Conference of the North American Chapter of the Association for Computational Linguistics (NAACL)","author":"Devlin Jacob","year":"2019","unstructured":"Jacob Devlin, Ming-Wei Chang, Kenton Lee, and Kristina Toutanova. 2019. BERT: Pre-training of deep bidirectional transformers for language understanding. In Annual Conference of the North American Chapter of the Association for Computational Linguistics (NAACL). 4171\u20134186."},{"issue":"8","key":"e_1_3_1_53_2","first-page":"9","article-title":"Language models are unsupervised multitask learners","volume":"1","author":"Radford Alec","year":"2019","unstructured":"Alec Radford, Jeffrey Wu, Rewon Child, David Luan, Dario Amodei, Ilya Sutskever, et\u00a0al. 2019. Language models are unsupervised multitask learners. OpenAI Blog 1, 8 (2019), 9.","journal-title":"OpenAI Blog"},{"key":"e_1_3_1_54_2","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2019.01157"}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3802577","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,6,12]],"date-time":"2026-06-12T11:47:19Z","timestamp":1781264839000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3802577"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,6,12]]},"references-count":53,"journal-issue":{"issue":"6","published-print":{"date-parts":[[2026,11,30]]}},"alternative-id":["10.1145\/3802577"],"URL":"https:\/\/doi.org\/10.1145\/3802577","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"value":"1084-4309","type":"print"},{"value":"1557-7309","type":"electronic"}],"subject":[],"published":{"date-parts":[[2026,6,12]]},"assertion":[{"value":"2024-09-19","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2026-02-28","order":2,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2026-06-12","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}