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Embed. Comput. Syst."],"published-print":{"date-parts":[[2026,7,31]]},"abstract":"<jats:p>Vector Symbolic Architectures (VSAs), also known as hyperdimensional (HD) computing, are increasingly deployed in cognitive applications due to their simple and efficient operations. The widespread adoption has, in turn, spurred the development of a diverse set of hardware solutions that optimize VSA performance for embedded and edge AI systems. Despite these advances, there remains a lack of comprehensive, unified discussion on the co-design and co-evolution of VSA algorithms and hardware. This survey aims at bridging that gap by linking theoretical, software-level explorations with efficient hardware architectures and emerging technology fabrics for VSAs, providing co-design insights that are accessible to both algorithm and hardware communities. First, we introduce the principles of vector-symbolic computing, including its core mathematical operations and learning paradigms. Second, we provide an in-depth discussion on hardware technologies for VSAs, analyzing analog, mixed-signal, and digital circuit design styles. We compare hardware implementations of VSAs by carrying out detailed analysis of their performance characteristics and tradeoffs, from which we distill design guidelines that are applicable across arbitrary VSA formulations. Third, we discuss a methodology for cross-layer design of VSAs that identifies synergies across layers and explores key ingredients for hardware\/software co-design of VSAs. Finally, as a concrete case study of this methodology, we present an in-memory computing hardware design for VSA-based hierarchical cognition, illustrating how the proposed co-design principles translate into efficient architectures. The article concludes with a discussion of open research challenges and opportunities for future explorations.<\/jats:p>","DOI":"10.1145\/3807784","type":"journal-article","created":{"date-parts":[[2026,4,9]],"date-time":"2026-04-09T11:25:57Z","timestamp":1775733957000},"page":"1-44","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["Cross-Layer Design of Vector-Symbolic Computing: Bridging Cognition and Brain-Inspired Hardware Acceleration"],"prefix":"10.1145","volume":"25","author":[{"ORCID":"https:\/\/orcid.org\/0009-0002-9128-7395","authenticated-orcid":false,"given":"Shuting","family":"Du","sequence":"first","affiliation":[{"name":"Purdue University","place":["West Lafayette, United States"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0278-4040","authenticated-orcid":false,"given":"Mohamed","family":"Ibrahim","sequence":"additional","affiliation":[{"name":"Georgia Institute of Technology","place":["Atlanta, United States"]},{"name":"The University of Texas at Dallas","place":["Atlanta, United States"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2982-5351","authenticated-orcid":false,"given":"Zishen","family":"Wan","sequence":"additional","affiliation":[{"name":"School of Electrical and Computer Engineering, Georgia Institute of Technology","place":["Atlanta, United States"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0001-5473-1381","authenticated-orcid":false,"given":"Luqi","family":"Zheng","sequence":"additional","affiliation":[{"name":"Purdue University","place":["West Lafayette, United States"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0000-3126-3899","authenticated-orcid":false,"given":"Boheng","family":"Zhao","sequence":"additional","affiliation":[{"name":"Purdue University","place":["West Lafayette, United States"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0007-8866-0773","authenticated-orcid":false,"given":"Zhenkun","family":"Fan","sequence":"additional","affiliation":[{"name":"Georgia Institute of Technology","place":["Atlanta, United States"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0003-9604-3987","authenticated-orcid":false,"given":"Che-kai","family":"Liu","sequence":"additional","affiliation":[{"name":"Georgia Institute of Technology","place":["Atlanta, United States"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5738-6942","authenticated-orcid":false,"given":"Tushar","family":"Krishna","sequence":"additional","affiliation":[{"name":"Georgia Institute of Technology","place":["Atlanta, United States"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8391-0576","authenticated-orcid":false,"given":"Arijit","family":"Raychowdhury","sequence":"additional","affiliation":[{"name":"Georgia Institute of Technology","place":["Atlanta, United States"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3393-9252","authenticated-orcid":false,"given":"Haitong","family":"Li","sequence":"additional","affiliation":[{"name":"Purdue University","place":["West Lafayette, United States"]}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2026,7,8]]},"reference":[{"key":"e_1_3_2_2_2","first-page":"1103","volume-title":"Proceedings of the 2022 IEEE 72nd Electronic Components and Technology Conference.","author":"Agarwal Rahul","year":"2022","unstructured":"Rahul Agarwal, Patrick Cheng, Priyal Shah, Brett Wilkerson, Raja Swaminathan, John Wuu, and Chandrasekhar Mandalapu. 2022. 3D packaging for heterogeneous integration. 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