{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,25]],"date-time":"2026-06-25T16:46:34Z","timestamp":1782405994575,"version":"3.54.5"},"reference-count":84,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2026,6,25]],"date-time":"2026-06-25T00:00:00Z","timestamp":1782345600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"}],"funder":[{"name":"PRISM"},{"DOI":"10.13039\/100000185","name":"DARPA","doi-asserted-by":"crossref","id":[{"id":"10.13039\/100000185","id-type":"DOI","asserted-by":"crossref"}]},{"name":"NSF","award":["PPoSS-2217071"],"award-info":[{"award-number":["PPoSS-2217071"]}]},{"name":"NSF I\/UCRC MIST Center","award":["IIP-1439644, IIP-1439680, IIP-1738752, IIP-1939009, IIP-1939050, and IIP-1939012"],"award-info":[{"award-number":["IIP-1439644, IIP-1439680, IIP-1738752, IIP-1939009, IIP-1939050, and IIP-1939012"]}]},{"DOI":"10.13039\/100004689","name":"Booz Allen Hamilton","doi-asserted-by":"crossref","award":["FA-8075-18-D-0004"],"award-info":[{"award-number":["FA-8075-18-D-0004"]}],"id":[{"id":"10.13039\/100004689","id-type":"DOI","asserted-by":"crossref"}]},{"name":"SRC","award":["2019-NM-2875"],"award-info":[{"award-number":["2019-NM-2875"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Archit. Code Optim."],"published-print":{"date-parts":[[2026,6,30]]},"abstract":"<jats:p>\n                    The disparity between processor speed and memory bandwidth has become a growing performance bottleneck, particularly for memory-intensive workloads. Processing-in-Memory (PIM) mitigates this bottleneck by integrating computation directly within DRAM. However, the effectiveness of PIM varies significantly across workloads, architectures, and DRAM technologies, yet it is often assessed using tightly coupled simulators and benchmarks that lack portability and generality. This article extends\n                    <jats:italic toggle=\"yes\">PIMbench<\/jats:italic>\n                    and\n                    <jats:italic toggle=\"yes\">PIMeval<\/jats:italic>\n                    \u2014a generalizable benchmark suite and an extensible PIM simulator to support a broader range of workloads, PIM architectures, and DRAM technologies. This evaluation incorporates roofline analysis and a breakdown of intra-memory execution stages to identify PIM-specific bottlenecks and performance scaling limits. The evaluation spans three classes of digital PIM architectures: subarray-level bit-serial, subarray-level bit-parallel, and bank-level bit-parallel. It further demonstrates how internal DRAM parameters such as subarray count and GDL width impact PIM performance. The code is publicly available at:\n                    <jats:ext-link xmlns:xlink=\"http:\/\/www.w3.org\/1999\/xlink\" xlink:href=\"https:\/\/github.com\/UVA-LavaLab\/PIMeval-PIMbench\">https:\/\/github.com\/UVA-LavaLab\/PIMeval-PIMbench<\/jats:ext-link>\n                    .\n                  <\/jats:p>","DOI":"10.1145\/3815581","type":"journal-article","created":{"date-parts":[[2026,5,13]],"date-time":"2026-05-13T11:38:38Z","timestamp":1778672318000},"page":"1-28","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Characterizing Digital DRAM PIM through Modeling and Benchmarking"],"prefix":"10.1145","volume":"23","author":[{"ORCID":"https:\/\/orcid.org\/0009-0002-2169-7380","authenticated-orcid":false,"given":"Farzana Ahmed","family":"Siddique","sequence":"first","affiliation":[{"name":"University of Virginia","place":["Charlottesville, United States"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0004-1756-1784","authenticated-orcid":false,"given":"Deyuan","family":"Guo","sequence":"additional","affiliation":[{"name":"University of Virginia","place":["Charlottesville, United States"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0005-1680-6863","authenticated-orcid":false,"given":"Hugo","family":"Abbot","sequence":"additional","affiliation":[{"name":"University of Virginia","place":["Charlottesville, United States"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0003-1788-3639","authenticated-orcid":false,"given":"Kyle","family":"Durrer","sequence":"additional","affiliation":[{"name":"University of Virginia","place":["Charlottesville, United States"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5549-2901","authenticated-orcid":false,"given":"Mohammadhosein","family":"Gholamrezaei","sequence":"additional","affiliation":[{"name":"University of Virginia","place":["Charlottesville, United States"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0004-0705-2820","authenticated-orcid":false,"given":"Morteza","family":"Baradaran","sequence":"additional","affiliation":[{"name":"University of Virginia","place":["Charlottesville, United States"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0005-2549-3926","authenticated-orcid":false,"given":"Ethan","family":"Ermovick","sequence":"additional","affiliation":[{"name":"University of Virginia","place":["Charlottesville, United States"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4203-5012","authenticated-orcid":false,"given":"Alif","family":"Ahmed","sequence":"additional","affiliation":[{"name":"University of Virginia","place":["Charlottesville, United States"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0008-3346-2136","authenticated-orcid":false,"given":"Zhenxing","family":"Fan","sequence":"additional","affiliation":[{"name":"University of Virginia","place":["Charlottesville, United States"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0004-2056-2761","authenticated-orcid":false,"given":"Beenish","family":"Gul","sequence":"additional","affiliation":[{"name":"University of Virginia","place":["Charlottesville, United States"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1959-8463","authenticated-orcid":false,"given":"Ashish","family":"Venkat","sequence":"additional","affiliation":[{"name":"University of Virginia","place":["Charlottesville, United States"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8091-9302","authenticated-orcid":false,"given":"Kevin","family":"Skadron","sequence":"additional","affiliation":[{"name":"University of Virginia","place":["Charlottesville, United States"]}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2026,6,25]]},"reference":[{"key":"e_1_3_2_2_2","doi-asserted-by":"publisher","DOI":"10.1145\/3357526.3357574"},{"key":"e_1_3_2_3_2","first-page":"662","volume-title":"ISCA","author":"Akhlaghi V.","year":"2018","unstructured":"V. Akhlaghi et\u00a0al. 2018. Snapea: Predictive early activation for reducing computation in deep convolutional neural networks. In ISCA. IEEE, 662\u2013673."},{"key":"e_1_3_2_4_2","doi-asserted-by":"publisher","DOI":"10.1145\/1465482.1465560"},{"key":"e_1_3_2_5_2","doi-asserted-by":"crossref","unstructured":"T. Andrulis J. S. Emer and V. Sze. 2024. CiMLoop: A flexible accurate and fast compute-in-memory modeling tool. arXiv:2405.07259 (2024).","DOI":"10.1109\/ISPASS61541.2024.00012"},{"key":"e_1_3_2_6_2","unstructured":"S. Beamer K. Asanovic and D. A. Patterson. Aug. 2015. The GAP benchmark suite. arXiv:1508.03619 (Aug. 2015.)."},{"key":"e_1_3_2_7_2","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_3_2_8_2","doi-asserted-by":"publisher","DOI":"10.1023\/A:1010933404324"},{"key":"e_1_3_2_9_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA51647.2021.00054"},{"key":"e_1_3_2_10_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446095"},{"key":"e_1_3_2_11_2","doi-asserted-by":"publisher","DOI":"10.1145\/3721145.3730420"},{"key":"e_1_3_2_12_2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1974.1050511"},{"key":"e_1_3_2_13_2","doi-asserted-by":"publisher","DOI":"10.1145\/3470496.3527431"},{"key":"e_1_3_2_14_2","unstructured":"DRAMsim3. 2025. DDR4-8Gb-x16-3200. Retrieved from https:\/\/github.com\/umd-memsys\/DRAMsim3\/blob\/master\/configs\/DDR4_8Gb_x16_3200.ini"},{"key":"e_1_3_2_15_2","unstructured":"DRAMsim3. 2025. GDDR5-1Gb-x32. Retrieved from https:\/\/github.com\/umd-memsys\/DRAMsim3\/blob\/master\/configs\/GDDR5_1Gb_x32.ini"},{"key":"e_1_3_2_16_2","unstructured":"DRAMsim3. 2025. GDDR5X-8Gb-x32. Retrieved from https:\/\/github.com\/umd-memsys\/DRAMsim3\/blob\/master\/configs\/GDDR5X_8Gb_x32.ini"},{"key":"e_1_3_2_17_2","doi-asserted-by":"publisher","DOI":"10.6028\/NIST.SP.800-38a"},{"key":"e_1_3_2_18_2","doi-asserted-by":"publisher","DOI":"10.1109\/54.748803"},{"key":"e_1_3_2_19_2","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000108"},{"key":"e_1_3_2_20_2","first-page":"155","volume-title":"European Conference on Parallel Processing","author":"Falevoz Yann","year":"2023","unstructured":"Yann Falevoz and Julien Legriel. 2023. Energy efficiency impact of processing in memory: A comprehensive review of workloads on the upmem architecture. In European Conference on Parallel Processing. Springer, 155\u2013166."},{"key":"e_1_3_2_21_2","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2017.3211117"},{"key":"e_1_3_2_22_2","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2002.1015506"},{"key":"e_1_3_2_23_2","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2019.2934048"},{"key":"e_1_3_2_24_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS57527.2023.00013"},{"key":"e_1_3_2_25_2","unstructured":"Deyuan Guo Mohammadhosein Gholamrezaei Matthew Hofmann Ashish Venkat Zhiru Zhang and Kevin Skadron. 2025. PIMsynth: A unified compiler framework for bit-serial processing-in-memory architectures. IEEE Computer Architecture Letters (2025)."},{"key":"e_1_3_2_26_2","doi-asserted-by":"publisher","DOI":"10.1109\/IGSC54211.2021.9651614"},{"key":"e_1_3_2_27_2","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2019.2911278"},{"key":"e_1_3_2_28_2","doi-asserted-by":"publisher","DOI":"10.1145\/3445814.3446749"},{"key":"e_1_3_2_29_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO61859.2024.00051"},{"key":"e_1_3_2_30_2","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.90"},{"key":"e_1_3_2_31_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO50266.2020.00040"},{"key":"e_1_3_2_32_2","doi-asserted-by":"publisher","DOI":"10.1145\/3282307"},{"key":"e_1_3_2_33_2","volume-title":"Hybrid Memory Cube Specification 2.1","author":"(HMCC) Hybrid Memory Cube Consortium","year":"2015","unstructured":"Hybrid Memory Cube Consortium (HMCC). 2015. Hybrid Memory Cube Specification 2.1. Retrieved from https:\/\/www.hybridmemorycube.org\/"},{"key":"e_1_3_2_34_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA57654.2024.00029"},{"key":"e_1_3_2_35_2","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2024.3493132"},{"key":"e_1_3_2_36_2","doi-asserted-by":"publisher","DOI":"10.1145\/2366231.2337202"},{"issue":"1","key":"e_1_3_2_37_2","first-page":"45","article-title":"Ramulator: A fast and extensible DRAM simulator","volume":"15","author":"Kim Y.","year":"2015","unstructured":"Y. Kim, W. Yang, and O. Mutlu. 2015. Ramulator: A fast and extensible DRAM simulator. CAL 15, 1 (2015), 45\u201349.","journal-title":"CAL"},{"key":"e_1_3_2_38_2","doi-asserted-by":"publisher","DOI":"10.1109\/HCS55958.2022.9895629"},{"key":"e_1_3_2_39_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42613.2021.9365862"},{"key":"e_1_3_2_40_2","unstructured":"Kyriazis George. 2012. Heterogeneous system architecture: A technical review. AMD Fusion Developer Summit (2012)."},{"key":"e_1_3_2_41_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO61859.2024.00053"},{"key":"e_1_3_2_42_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA52012.2021.00013"},{"key":"e_1_3_2_43_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA47549.2020.00052"},{"key":"e_1_3_2_44_2","first-page":"218","volume-title":"ISCA","author":"Lenjani M.","year":"2022","unstructured":"M. Lenjani et\u00a0al. 2022. Gearbox: A case for supporting accumulation dispatching and hybrid partitioning in PIM-based accelerators. In ISCA. 218\u2013230."},{"issue":"2","key":"e_1_3_2_45_2","first-page":"109","article-title":"Pulley: An algorithm\/hardware co-optimization for in-memory sorting","volume":"21","author":"Lenjani M.","year":"2022","unstructured":"M. Lenjani, A. Ahmed, and K. Skadron. 2022. Pulley: An algorithm\/hardware co-optimization for in-memory sorting. CAL 21, 2 (2022), 109\u2013112.","journal-title":"CAL"},{"key":"e_1_3_2_46_2","unstructured":"Jure Leskovec and Julian Mcauley. 2012. Learning to discover social circles in ego networks. Advances in Neural Information Processing Systems 25 (2012)."},{"key":"e_1_3_2_47_2","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3123977"},{"issue":"2","key":"e_1_3_2_48_2","first-page":"106","article-title":"DRAMsim3: A cycle-accurate, thermal-capable DRAM simulator","volume":"19","author":"Li S.","year":"2020","unstructured":"S. Li et\u00a0al. 2020. DRAMsim3: A cycle-accurate, thermal-capable DRAM simulator. CAL 19, 2 (2020), 106\u2013109.","journal-title":"CAL"},{"key":"e_1_3_2_49_2","doi-asserted-by":"publisher","DOI":"10.1145\/3240302.3240315"},{"key":"e_1_3_2_50_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA59077.2024.00020"},{"key":"e_1_3_2_51_2","doi-asserted-by":"crossref","unstructured":"H\u00e9ctor Mart\u0131nez Juan G\u00f3mez-Luna Rafael Palomar and Joaqu\u00edn Olivares. 2026. In-memory operators for medical image processing. Future Generation Computer Systems 174 (2026) 107939.","DOI":"10.1016\/j.future.2025.107939"},{"key":"e_1_3_2_52_2","unstructured":"C. J. Micron. 2017. TN-40-07: Calculating memory power for DDR4 SDRAM."},{"key":"e_1_3_2_53_2","unstructured":"Micron. 2025. Integrating and Operating HBM Memory. Retrieved from https:\/\/assets.micron.com\/adobe\/assets\/urn:aaid:aem:275edf31-79e3-4b6c-8bbd-a233babe9281\/original\/as\/micron-hbm2e-memory-wp.pdf"},{"key":"e_1_3_2_54_2","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.1998.658762"},{"key":"e_1_3_2_55_2","doi-asserted-by":"publisher","DOI":"10.1002\/widm.53"},{"key":"e_1_3_2_56_2","first-page":"171","volume-title":"Emerging Computing: From Devices to Systems: Looking Beyond Moore and Von Neumann","author":"Mutlu O.","year":"2022","unstructured":"O. Mutlu, S. Ghose, J. G\u00f3mez-Luna, and R. Ausavarungnirun. 2022. A modern primer on processing in memory. In Emerging Computing: From Devices to Systems: Looking Beyond Moore and Von Neumann. Springer, 171\u2013243."},{"key":"e_1_3_2_57_2","unstructured":"NVIDIA Corporation. 2020. NVIDIA A100 Tensor Core GPU. Retrieved from https:\/\/www.nvidia.com\/en-us\/data-center\/a100\/. Accessed: 2024-06-02."},{"key":"e_1_3_2_58_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA52012.2021.00078"},{"key":"e_1_3_2_59_2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-30117-2_112"},{"key":"e_1_3_2_60_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA57654.2024.00024"},{"key":"e_1_3_2_61_2","doi-asserted-by":"publisher","DOI":"10.1109\/40.592312"},{"key":"e_1_3_2_62_2","unstructured":"Samsung. 2025. PIMSimulator. Retrieved from https:\/\/github.com\/SAITPublic\/PIMSimulator. Accessed June 4 2025."},{"key":"e_1_3_2_63_2","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3124544"},{"key":"e_1_3_2_64_2","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC63097.2024.00030"},{"key":"e_1_3_2_65_2","article-title":"Very deep convolutional networks for large-scale image recognition","author":"Simonyan K.","year":"2014","unstructured":"K. Simonyan and A. Zisserman. 2014. Very deep convolutional networks for large-scale image recognition. arXiv preprint arXiv:1409.1556 (2014).","journal-title":"arXiv preprint arXiv:1409.1556"},{"key":"e_1_3_2_66_2","volume-title":"AXDIMM: Acceleration DIMM Specification","author":"Inc. SK hynix","year":"2023","unstructured":"SK hynix Inc.2023. AXDIMM: Acceleration DIMM Specification. Retrieved from https:\/\/www.skhynix.com\/"},{"key":"e_1_3_2_67_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA61900.2025.00116"},{"key":"e_1_3_2_68_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1970.5008902"},{"key":"e_1_3_2_69_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA52012.2021.00027"},{"key":"e_1_3_2_70_2","unstructured":"TechPowerUp. 2025. AMD EPYC Processors. Retrieved from https:\/\/www.techpowerup.com\/cpu-specs\/?f=generation_AMD+EPYC. Accessed June 4 2025."},{"key":"e_1_3_2_71_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA59077.2024.00052"},{"key":"e_1_3_2_72_2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-41321-1_11"},{"key":"e_1_3_2_73_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2021.3131049"},{"key":"e_1_3_2_74_2","doi-asserted-by":"publisher","DOI":"10.1145\/2851141.2851145"},{"key":"e_1_3_2_75_2","unstructured":"Wikipedia. 2025. Nvidia GPUs. Retrieved from https:\/\/en.wikipedia.org\/wiki\/List_of_Nvidia_graphics_processing_units. Accessed June 4 2025."},{"key":"e_1_3_2_76_2","doi-asserted-by":"publisher","DOI":"10.1145\/1498765.1498785"},{"key":"e_1_3_2_77_2","first-page":"251","volume-title":"ISCA","author":"Wu L.","year":"2021","unstructured":"L. Wu et\u00a0al. 2021. Sieve: Scalable in-situ DRAM-based accelerator designs for massively parallel k-mer matching. In ISCA. 251\u2013264."},{"key":"e_1_3_2_78_2","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2022.3201168"},{"key":"e_1_3_2_79_2","doi-asserted-by":"publisher","DOI":"10.1145\/216585.216588"},{"key":"e_1_3_2_80_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA61900.2025.00054"},{"issue":"1","key":"e_1_3_2_81_2","first-page":"6","article-title":"PIMSim: A flexible and detailed processing-in-memory simulator","volume":"18","author":"Xu S.","year":"2018","unstructured":"S. Xu, X. Chen, Y. Wang, Y. Han, X. Qian, and X. Li. 2018. PIMSim: A flexible and detailed processing-in-memory simulator. CAL 18, 1 (2018), 6\u20139.","journal-title":"CAL"},{"key":"e_1_3_2_82_2","unstructured":"Y. Zhou and others. 2005. SiO2 Matrix from PARSEC Collection in SuiteSparse Matrix Collection. Retrieved from https:\/\/sparse.tamu.edu\/PARSEC\/SiO2"},{"key":"e_1_3_2_83_2","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306783"},{"issue":"1","key":"e_1_3_2_84_2","first-page":"54","article-title":"Multipim: A detailed and configurable multi-stack processing-in-memory simulator","volume":"20","author":"Yu C.","year":"2021","unstructured":"C. Yu, S. Liu, and S. Khan. 2021. Multipim: A detailed and configurable multi-stack processing-in-memory simulator. CAL 20, 1 (2021), 54\u201357.","journal-title":"CAL"},{"key":"e_1_3_2_85_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA56546.2023.10071005"}],"container-title":["ACM Transactions on Architecture and Code Optimization"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3815581","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,6,25]],"date-time":"2026-06-25T15:54:18Z","timestamp":1782402858000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3815581"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,6,25]]},"references-count":84,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2026,6,30]]}},"alternative-id":["10.1145\/3815581"],"URL":"https:\/\/doi.org\/10.1145\/3815581","relation":{},"ISSN":["1544-3566","1544-3973"],"issn-type":[{"value":"1544-3566","type":"print"},{"value":"1544-3973","type":"electronic"}],"subject":[],"published":{"date-parts":[[2026,6,25]]},"assertion":[{"value":"2025-06-18","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2026-05-03","order":2,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2026-06-25","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}