{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,8,29]],"date-time":"2026-08-29T16:18:36Z","timestamp":1788020316372,"version":"build-2784847793"},"reference-count":85,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2026,8,29]],"date-time":"2026-08-29T00:00:00Z","timestamp":1787961600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"}],"funder":[{"name":"National Key Research and Development Program of China","award":["2024YFE0204300"],"award-info":[{"award-number":["2024YFE0204300"]}]},{"name":"National Program for Support of Top-notch Young Professionals of China","award":["24Z130300727"],"award-info":[{"award-number":["24Z130300727"]}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"crossref","award":["62402311, 62072262, 61834006"],"award-info":[{"award-number":["62402311, 62072262, 61834006"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"crossref"}]},{"name":"Natural Science Foundation of Shanghai","award":["24ZR1433700"],"award-info":[{"award-number":["24ZR1433700"]}]},{"name":"Key Research and Development Program of Shanghai","award":["25LN3201200"],"award-info":[{"award-number":["25LN3201200"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Archit. Code Optim."],"published-print":{"date-parts":[[2026,9,30]]},"abstract":"<jats:p>\n                    DRAM-based Processing-in-Memory (PIM) addresses the \u201cmemory wall\u201d by executing computations directly inside main memory. However, memory interleaving and virtual memory limit contiguous data size visible to PIM units, constraining PIM task granularity. Fine-grained PIM tasks incur significant offloading overhead that negates PIM performance benefits. To mitigate this, existing PIM systems drastically isolate PIM memory or disable memory interleaving. These design choices, however, decrease the CPU memory bandwidth and introduce extra data transfer, leading to an additional \u201csystem memory wall\u201d that degrades CPU performance and must be resolved to realize PIM\u2019s full potential. In this work, we propose GUMPIM, a\n                    <jats:underline>PIM<\/jats:underline>\n                    system that allows interleaved CPU pages and non-interleaved PIM pages to coexist in a\n                    <jats:underline>U<\/jats:underline>\n                    nitary and\n                    <jats:underline>M<\/jats:underline>\n                    alleable memory space with\n                    <jats:underline>G<\/jats:underline>\n                    uaranteed PIM page allocation. GUMPIM enables zero-copy during PIM task offloading and maintains CPU memory bandwidth while ensuring low PIM offloading overhead. First, we propose a dual-track memory management mechanism consisting of independent page allocation and address translation for CPU and PIM pages. Second, we design GUMPIM interface hardware on PIM-enabled DRAMs to provide a dynamic address mapping for the different data layouts of CPU and PIM pages. Third, we propose a PIM-assisted page migration mechanism that transparently migrates pages while preserving CPU access bandwidth, thereby enabling guaranteed and accelerated PIM page allocation. GUMPIM requires no changes to commodity DRAM standards; all hardware modifications are limited to the DRAM side, ensuring full compatibility with existing CPUs and enabling immediate deployment on current HBMx- and LPDDRx-based PIM platforms. Our results show only &lt;0.1% performance degradation for CPU workloads on GUMPIM, in contrast to the 25.8% degradation on PIM systems with memory interleaving turned off. For PIM workloads, GUMPIM reduces memory allocation and CPU-part computation times by 2.7\u00d7 and 4.93\u00d7, respectively, yielding an end-to-end 2.3\u00d7 speedup over a state-of-the-art baseline system.\n                  <\/jats:p>","DOI":"10.1145\/3833426","type":"journal-article","created":{"date-parts":[[2026,8,8]],"date-time":"2026-08-08T09:12:51Z","timestamp":1786180371000},"page":"1-25","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["GUMPIM: Unitary and Malleable Memory for Processing-in-Memory with Guaranteed PIM Pages"],"prefix":"10.1145","volume":"23","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-8291-6896","authenticated-orcid":false,"given":"Yilong","family":"Zhao","sequence":"first","affiliation":[{"name":"Shanghai Jiao Tong University","place":["Shanghai, China"]},{"name":"Shanghai Qi Zhi Institute","place":["Shanghai, China"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8769-293X","authenticated-orcid":false,"given":"Fangxin","family":"Liu","sequence":"additional","affiliation":[{"name":"Shanghai Jiaotong University","place":["Shanghai, China"]},{"name":"Shanghai Qi Zhi Institute","place":["Shanghai, China"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0000-1535-8046","authenticated-orcid":false,"given":"Yiwei","family":"Hu","sequence":"additional","affiliation":[{"name":"Shanghai Jiao Tong University","place":["Shanghai, China"]},{"name":"Shanghai Qi Zhi Institute","place":["Shanghai, China"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0003-2157-4927","authenticated-orcid":false,"given":"Zongwu","family":"Wang","sequence":"additional","affiliation":[{"name":"Shanghai Jiao Tong University","place":["Shanghai, China"]},{"name":"Shanghai Qi Zhi Institute","place":["Shanghai, China"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8433-7281","authenticated-orcid":false,"given":"Mingyu","family":"Gao","sequence":"additional","affiliation":[{"name":"Tsinghua University","place":["Beijing, China"]},{"name":"Shanghai Qi Zhi Institute","place":["Beijing, China"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0075-2312","authenticated-orcid":false,"given":"Onur","family":"Mutlu","sequence":"additional","affiliation":[{"name":"ETH Z\u00fcrich","place":["Z\u00fcrich, Switzerland"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0008-2099-4109","authenticated-orcid":false,"given":"He","family":"Xian","sequence":"additional","affiliation":[{"name":"Shanghai Qi Zhi Institute","place":["Shanghai, China"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0003-1196-661X","authenticated-orcid":false,"given":"Hanlin","family":"Dong","sequence":"additional","affiliation":[{"name":"Shanghai Qi Zhi Institute","place":["Shanghai, China"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8417-5796","authenticated-orcid":false,"given":"Naifeng","family":"Jing","sequence":"additional","affiliation":[{"name":"Shanghai Jiao Tong University","place":["Shanghai, China"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2790-5884","authenticated-orcid":false,"given":"Xiaoyao","family":"Liang","sequence":"additional","affiliation":[{"name":"Shanghai Jiao Tong University","place":["Shanghai, China"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4714-7400","authenticated-orcid":false,"given":"Haibing","family":"Guan","sequence":"additional","affiliation":[{"name":"Shanghai Jiao Tong University","place":["Shanghai, China"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6747-126X","authenticated-orcid":false,"given":"Qiang","family":"Xu","sequence":"additional","affiliation":[{"name":"The Chinese University of Hong Kong","place":["Hong Kong, China"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5980-4236","authenticated-orcid":false,"given":"Chixiao","family":"Chen","sequence":"additional","affiliation":[{"name":"Fudan University","place":["Shanghai, China"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5917-1264","authenticated-orcid":false,"given":"Shuxue","family":"Quan","sequence":"additional","affiliation":[{"name":"Yizhu Technology Co., Ltd.","place":["Suzhou, China"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8588-9483","authenticated-orcid":false,"given":"Tao","family":"Yang","sequence":"additional","affiliation":[{"name":"Huawei Technologies Co Ltd","place":["Shenzhen, China"]},{"name":"Shanghai Jiao Tong University","place":["Shenzhen, China"]},{"name":"Shanghai Qi Zhi Institute","place":["Shenzhen, China"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7353-8798","authenticated-orcid":false,"given":"Li","family":"Jiang","sequence":"additional","affiliation":[{"name":"Shanghai Jiao Tong University","place":["Shanghai, China"]},{"name":"Shanghai Qi Zhi Institute","place":["Shanghai, China"]}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2026,8,29]]},"reference":[{"key":"e_1_3_1_2_2","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750386"},{"key":"e_1_3_1_3_2","doi-asserted-by":"publisher","DOI":"10.1093\/bioinformatics\/btae631"},{"issue":"2","key":"e_1_3_1_4_2","first-page":"14","article-title":"CACTI 7: New tools for interconnect exploration in innovative off-chip memories","volume":"14","author":"Balasubramonian Rajeev","year":"2017","unstructured":"Rajeev Balasubramonian et\u00a0al. 2017. CACTI 7: New tools for interconnect exploration in innovative off-chip memories. ACM TACO 14, 2, Article 14 (2017).","journal-title":"ACM TACO"},{"key":"e_1_3_1_5_2","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC66894.2025.00030"},{"key":"e_1_3_1_6_2","volume-title":"The GAP Benchmark Suite","author":"Beamer Scott","year":"2017","unstructured":"Scott Beamer et\u00a0al. 2017. The GAP Benchmark Suite. arXiv preprint arXiv:1508.03619"},{"key":"e_1_3_1_7_2","doi-asserted-by":"publisher","DOI":"10.1145\/3466752.3480133"},{"key":"e_1_3_1_8_2","doi-asserted-by":"publisher","DOI":"10.1145\/3173162.3173177"},{"key":"e_1_3_1_9_2","volume-title":"ISCA","author":"Boroumand Amirali","year":"2019","unstructured":"Amirali Boroumand et\u00a0al. 2019. CoNDA: Efficient cache coherence support for near-data accelerators. In ISCA."},{"key":"e_1_3_1_10_2","doi-asserted-by":"publisher","DOI":"10.1109\/PACT52795.2021.00019"},{"key":"e_1_3_1_11_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICDE53745.2022.00270"},{"key":"e_1_3_1_12_2","volume-title":"ISCA","author":"Chen Dan","year":"2023","unstructured":"Dan Chen et\u00a0al. 2023. MetaNMP: Leveraging cartesian-like product to accelerate HGNNs with near-memory processing. In ISCA."},{"key":"e_1_3_1_13_2","volume-title":"PACT","author":"Chen Jinfan","year":"2024","unstructured":"Jinfan Chen et\u00a0al. 2024. SimplePIM: A software framework for productive and efficient processing-in-memory. In PACT."},{"key":"e_1_3_1_14_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA61900.2025.00047"},{"key":"e_1_3_1_15_2","volume-title":"ITC-CSCC","author":"Choi Jaeyoon","year":"2015","unstructured":"Jaeyoon Choi et\u00a0al. 2015. A study in identifying memory address interleaving of x86 servers. In ITC-CSCC."},{"key":"e_1_3_1_16_2","volume-title":"Ramulator V2.0a","year":"2023","unstructured":"CMU-SAFARI. 2023. Ramulator V2.0a. Retrieved November 5, 2025 from https:\/\/github.com\/CMU-SAFARI\/ramulator2"},{"key":"e_1_3_1_17_2","volume-title":"ICS","author":"Junior Geraldo Francisco de Oliveira","year":"2025","unstructured":"Geraldo Francisco de Oliveira Junior et\u00a0al. 2025. Proteus: Achieving high-performance processing-using-DRAM with dynamic bit-precision, adaptive data representation, and flexible arithmetic. In ICS."},{"key":"e_1_3_1_18_2","doi-asserted-by":"publisher","DOI":"10.1109\/HOTCHIPS.2019.8875680"},{"key":"e_1_3_1_19_2","volume-title":"ISCA","author":"Devic Alexandar","year":"2022","unstructured":"Alexandar Devic et\u00a0al. 2022. To PIM or not for emerging general purpose processing in DDR memory systems. In ISCA."},{"key":"e_1_3_1_20_2","doi-asserted-by":"publisher","DOI":"10.1093\/bioinformatics\/btad155"},{"key":"e_1_3_1_21_2","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2015.22"},{"key":"e_1_3_1_22_2","doi-asserted-by":"publisher","DOI":"10.1145\/3037697.3037702"},{"key":"e_1_3_1_23_2","volume-title":"USENIX ATC","author":"Gaud Fabien","year":"2014","unstructured":"Fabien Gaud et\u00a0al. 2014. Large pages may be harmful on NUMA systems. In USENIX ATC."},{"key":"e_1_3_1_24_2","doi-asserted-by":"publisher","DOI":"10.1145\/2989081.2989102"},{"key":"e_1_3_1_25_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI54635.2022.00063"},{"key":"e_1_3_1_26_2","doi-asserted-by":"publisher","DOI":"10.1145\/3700434"},{"key":"e_1_3_1_27_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS61541.2024.00029"},{"key":"e_1_3_1_28_2","doi-asserted-by":"publisher","DOI":"10.5555\/983550"},{"key":"e_1_3_1_29_2","doi-asserted-by":"publisher","DOI":"10.1145\/3676641.3716267"},{"key":"e_1_3_1_30_2","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC59245.2023.00030"},{"key":"e_1_3_1_31_2","doi-asserted-by":"publisher","DOI":"10.1109\/IGSC54211.2021.9651614"},{"key":"e_1_3_1_32_2","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2022.3174101"},{"key":"e_1_3_1_33_2","volume-title":"ISPASS","author":"G\u00f3mez-Luna Juan","year":"2023","unstructured":"Juan G\u00f3mez-Luna et\u00a0al. 2023. Evaluating machine learning workloads on memory-centric computing systems. In ISPASS."},{"key":"e_1_3_1_34_2","doi-asserted-by":"publisher","DOI":"10.1145\/3445814.3446749"},{"key":"e_1_3_1_35_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO50266.2020.00040"},{"key":"e_1_3_1_36_2","doi-asserted-by":"publisher","DOI":"10.1145\/3676641.3716009"},{"key":"e_1_3_1_37_2","doi-asserted-by":"publisher","DOI":"10.1145\/1186736.1186737"},{"key":"e_1_3_1_38_2","unstructured":"Marius Hillenbrand. 2017. Physical Address Decoding in Intel Xeon v3\/v4 CPUs: A Supplemental Datasheet. Retrieved from https:\/\/os.itec.kit.edu\/downloads\/publ_2017_hillenbrand_xeon_decoding.pdf"},{"key":"e_1_3_1_39_2","doi-asserted-by":"publisher","DOI":"10.1145\/3124680.3124742"},{"key":"e_1_3_1_40_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2016.7753257"},{"key":"e_1_3_1_41_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS57527.2023.00031"},{"key":"e_1_3_1_42_2","volume-title":"Memory Systems: Cache, DRAM, Disk","author":"Jacob B.","year":"2010","unstructured":"B. Jacob et\u00a0al. 2010. Memory Systems: Cache, DRAM, Disk. Elsevier Science."},{"key":"e_1_3_1_43_2","volume-title":"LPDDR5 SDRAM Standard","year":"2020","unstructured":"JEDEC. 2020. LPDDR5 SDRAM Standard. Technical Report. Retrieved from https:\/\/www.jedec.org\/standards-documents\/docs\/jesd209-5a"},{"key":"e_1_3_1_44_2","volume-title":"DDR4 SDRAM Standard","year":"2021","unstructured":"JEDEC. 2021. DDR4 SDRAM Standard. Technical Report. Retrieved from https:\/\/www.jedec.org\/standards-documents\/docs\/jesd79-4a"},{"key":"e_1_3_1_45_2","volume-title":"High Bandwidth Memory (HBM3) DRAM","year":"2023","unstructured":"JEDEC. 2023. High Bandwidth Memory (HBM3) DRAM. Technical Report. Retrieved from https:\/\/www.jedec.org\/standards-documents\/docs\/jesd238a"},{"key":"e_1_3_1_46_2","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429446"},{"key":"e_1_3_1_47_2","first-page":"66","article-title":"PIM-Tree: A skew-resistant index for processing-in-memory","volume":"34","author":"Kang Hongbo","year":"2022","unstructured":"Hongbo Kang et\u00a0al. 2022. PIM-Tree: A skew-resistant index for processing-in-memory. Proc. VLDB Endow. 34, Article 66 (2022).","journal-title":"Proc. VLDB Endow."},{"key":"e_1_3_1_48_2","volume-title":"ISCA","author":"Ke Liu","year":"2020","unstructured":"Liu Ke et\u00a0al. 2020. RecNMP: Accelerating personalized recommendation with near-memory processing. In ISCA."},{"key":"e_1_3_1_49_2","doi-asserted-by":"publisher","DOI":"10.1109\/HCS52781.2021.9567191"},{"key":"e_1_3_1_50_2","doi-asserted-by":"publisher","DOI":"10.1186\/s12864-018-4460-0"},{"key":"e_1_3_1_51_2","doi-asserted-by":"publisher","DOI":"10.1109\/EPEPS47316.2019.193209"},{"key":"e_1_3_1_52_2","volume-title":"ISCA","author":"Kim Yoongu","year":"2012","unstructured":"Yoongu Kim et\u00a0al. 2012. A case for exploiting subarray-level parallelism (SALP) in DRAM. In ISCA."},{"key":"e_1_3_1_53_2","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2015.2414456"},{"key":"e_1_3_1_54_2","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358284"},{"key":"e_1_3_1_55_2","doi-asserted-by":"publisher","DOI":"10.1109\/HCS55958.2022.9895629"},{"key":"e_1_3_1_56_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42613.2021.9365862"},{"key":"e_1_3_1_57_2","volume-title":"DaMoN","author":"Lee Donghun","year":"2022","unstructured":"Donghun Lee et\u00a0al. 2022. Improving in-memory database operations with acceleration DIMM (AxDIMM). In DaMoN."},{"key":"e_1_3_1_58_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA68181.2026.11408588"},{"key":"e_1_3_1_59_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA56546.2023.10071054"},{"key":"e_1_3_1_60_2","volume-title":"ISCA","author":"Liu Yuxi","year":"2018","unstructured":"Yuxi Liu et\u00a0al. 2018. Get out of the valley: Power-efficient address mapping for GPUs. In ISCA."},{"key":"e_1_3_1_61_2","volume-title":"The gem5 Simulator: Version 20.0+","author":"Lowe-Power Jason","year":"2020","unstructured":"Jason Lowe-Power et\u00a0al. 2020. The gem5 Simulator: Version 20.0+. arXiv preprint arXiv:2007.03152"},{"issue":"1","key":"e_1_3_1_62_2","first-page":"112","article-title":"Ramulator 2.0: A modern, modular, and extensible DRAM simulator","volume":"23","author":"Luo Haocong","year":"2024","unstructured":"Haocong Luo et\u00a0al. 2024. Ramulator 2.0: A modern, modular, and extensible DRAM simulator. CAL 23, 1 (2024), 112\u2013116.","journal-title":"CAL"},{"key":"e_1_3_1_63_2","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155664"},{"key":"e_1_3_1_64_2","article-title":"NVIDIA Collective Communication Library (NCCL) Documentation","year":"2020","unstructured":"Nvidia. 2020. NVIDIA Collective Communication Library (NCCL) Documentation. Retrieved from https:\/\/docs.nvidia.com\/deeplearning\/nccl\/user-guide\/docs\/usage\/p2p.html","journal-title":"https:\/\/docs.nvidia.com\/deeplearning\/nccl\/user-guide\/docs\/usage\/p2p.html"},{"issue":"1","key":"e_1_3_1_65_2","first-page":"8","article-title":"PiDRAM: A holistic end-to-end FPGA-based framework for Processing-in-DRAM","volume":"20","author":"Olgun Ataberk","year":"2022","unstructured":"Ataberk Olgun et\u00a0al. 2022. PiDRAM: A holistic end-to-end FPGA-based framework for Processing-in-DRAM. TACO 20, 1, Article 8 (2022).","journal-title":"TACO"},{"key":"e_1_3_1_66_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA57654.2024.00024"},{"key":"e_1_3_1_67_2","doi-asserted-by":"publisher","DOI":"10.1145\/3297858.3304064"},{"key":"e_1_3_1_68_2","volume-title":"SEC","author":"Pessl Peter","year":"2016","unstructured":"Peter Pessl et\u00a0al. 2016. DRAMA: Exploiting dram addressing for cross-cpu attacks. In SEC."},{"key":"e_1_3_1_69_2","volume-title":"Extend the Memory Map","author":"Inc. Qualcomm Technologies,","year":"2026","unstructured":"Qualcomm Technologies, Inc.2026. Extend the Memory Map. Retrieved February 12, 2026 from https:\/\/docs.qualcomm.com\/doc\/80-70018-3\/topic\/customize.html#extend-the-memory-map"},{"key":"e_1_3_1_70_2","volume-title":"4RCD0232K: DDR4 Registering Clock Driver (RCD)","author":"Corporation Renesas Electronics","year":"2024","unstructured":"Renesas Electronics Corporation. 2024. 4RCD0232K: DDR4 Registering Clock Driver (RCD). Retrieved November 12, 2023 from https:\/\/www.renesas.com\/en\/products\/4rcd0232k"},{"key":"e_1_3_1_71_2","doi-asserted-by":"publisher","DOI":"10.1145\/3656019.3676947"},{"key":"e_1_3_1_72_2","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540725"},{"key":"e_1_3_1_73_2","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3124544"},{"key":"e_1_3_1_74_2","volume-title":"M5ops Documentation","author":"Developers The gem5","year":"2026","unstructured":"The gem5 Developers. 2026. M5ops Documentation. Retrieved February 5, 2026 from https:\/\/www.gem5.org\/documentation\/general_docs\/m5ops\/"},{"key":"e_1_3_1_75_2","volume-title":"Hugetlbfs Reservation","author":"Developers The Linux Kernel","year":"2019","unstructured":"The Linux Kernel Developers. 2019. Hugetlbfs Reservation. Retrieved February 5, 2026 from https:\/\/www.kernel.org\/doc\/html\/v5.1\/vm\/hugetlbfs_reserv.html"},{"key":"e_1_3_1_76_2","article-title":"UPMEM DPU SDK 2023.2.0 Documentation","year":"2023","unstructured":"UPMEM. 2023. UPMEM DPU SDK 2023.2.0 Documentation. Retrieved from https:\/\/sdk.upmem.com\/2023.2.0\/","journal-title":"https:\/\/sdk.upmem.com\/2023.2.0\/"},{"key":"e_1_3_1_77_2","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218599"},{"key":"e_1_3_1_78_2","volume-title":"DATE","author":"Wei Yizhou","year":"2022","unstructured":"Yizhou Wei et\u00a0al. 2022. PIMProf: An automated program profiler for processing-in-memory offloading decisions. In DATE."},{"key":"e_1_3_1_79_2","doi-asserted-by":"publisher","DOI":"10.1145\/216585.216588"},{"key":"e_1_3_1_80_2","volume-title":"SEC","author":"Xiao Yuan","year":"2016","unstructured":"Yuan Xiao et\u00a0al. 2016. One bit flips, one cloud flops: Cross-VM row hammer attacks and privilege escalation. In SEC."},{"key":"e_1_3_1_81_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA51647.2021.00055"},{"key":"e_1_3_1_82_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA57654.2024.00030"},{"key":"e_1_3_1_83_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.phpro.2012.05.169"},{"key":"e_1_3_1_84_2","doi-asserted-by":"publisher","DOI":"10.1145\/3503222.3507774"},{"key":"e_1_3_1_85_2","volume-title":"ISCA","author":"Zhao Kaiyang","year":"2023","unstructured":"Kaiyang Zhao et\u00a0al. 2023. Contiguitas: The pursuit of physical memory contiguity in datacenters. In ISCA."},{"key":"e_1_3_1_86_2","volume-title":"ISCA","author":"Zhao Yilong","year":"2024","unstructured":"Yilong Zhao et\u00a0al. 2024. UM-PIM: DRAM-based PIM with uniform & shared memory space. In ISCA."}],"container-title":["ACM Transactions on Architecture and Code Optimization"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3833426","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,8,29]],"date-time":"2026-08-29T15:47:23Z","timestamp":1788018443000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3833426"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,8,29]]},"references-count":85,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2026,9,30]]}},"alternative-id":["10.1145\/3833426"],"URL":"https:\/\/doi.org\/10.1145\/3833426","relation":{},"ISSN":["1544-3566","1544-3973"],"issn-type":[{"value":"1544-3566","type":"print"},{"value":"1544-3973","type":"electronic"}],"subject":[],"published":{"date-parts":[[2026,8,29]]},"assertion":[{"value":"2026-03-25","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2026-05-21","order":2,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2026-08-29","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}