{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:44:42Z","timestamp":1750308282526,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":22,"publisher":"ACM","license":[{"start":{"date-parts":[[2002,2,24]],"date-time":"2002-02-24T00:00:00Z","timestamp":1014508800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2002,2,24]]},"DOI":"10.1145\/503048.503050","type":"proceedings-article","created":{"date-parts":[[2004,4,19]],"date-time":"2004-04-19T17:18:43Z","timestamp":1082395123000},"page":"3-10","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":15,"title":["Interconnect enhancements for a high-speed PLD architecture"],"prefix":"10.1145","author":[{"given":"Michael","family":"Hutton","sequence":"first","affiliation":[{"name":"Altera Corporation, San Jose, CA"}]},{"given":"Vinson","family":"Chan","sequence":"additional","affiliation":[{"name":"Altera Corporation, San Jose, CA"}]},{"given":"Peter","family":"Kazarian","sequence":"additional","affiliation":[{"name":"Altera Corporation, San Jose, CA"}]},{"given":"Victor","family":"Maruri","sequence":"additional","affiliation":[{"name":"Altera Corporation, San Jose, CA"}]},{"given":"Tony","family":"Ngai","sequence":"additional","affiliation":[{"name":"Altera Corporation, San Jose, CA"}]},{"given":"Jim","family":"Park","sequence":"additional","affiliation":[{"name":"Altera Corporation, San Jose, CA"}]},{"given":"Rakesh","family":"Patel","sequence":"additional","affiliation":[{"name":"Altera Corporation, San Jose, CA"}]},{"given":"Bruce","family":"Pedersen","sequence":"additional","affiliation":[{"name":"Altera Corporation, San Jose, CA"}]},{"given":"Jay","family":"Schleicher","sequence":"additional","affiliation":[{"name":"Altera Corporation, San Jose, CA"}]},{"given":"Sergey","family":"Shumarayev","sequence":"additional","affiliation":[{"name":"Altera Corporation, San Jose, CA"}]}],"member":"320","published-online":{"date-parts":[[2002,2,24]]},"reference":[{"key":"e_1_3_2_1_1_2","doi-asserted-by":"publisher","DOI":"10.1145\/329166.329171"},{"key":"e_1_3_2_1_2_2","unstructured":"Altera Corp. http:\/\/www.altera.com.  Altera Corp. http:\/\/www.altera.com."},{"key":"e_1_3_2_1_3_2","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1999.777267"},{"key":"e_1_3_2_1_4_2","doi-asserted-by":"publisher","DOI":"10.5555\/113938.149490"},{"key":"e_1_3_2_1_5_2","doi-asserted-by":"publisher","DOI":"10.1145\/275107.275116"},{"key":"e_1_3_2_1_6_2","doi-asserted-by":"publisher","DOI":"10.1145\/275107.275142"},{"key":"e_1_3_2_1_7_2","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296415"},{"key":"e_1_3_2_1_8_2","doi-asserted-by":"publisher","DOI":"10.1145\/329166.329173"},{"key":"e_1_3_2_1_9_2","unstructured":"W-J. Huang M. Hutton V. Maruri T. Ngai R. Patel B. Pedersen J. Schleicher and S. Shumarayev \"PLD Routing Architecture with Both Fast and Regular Routing Resources\" US Patent Application Pending.  W-J. Huang M. Hutton V. Maruri T. Ngai R. Patel B. Pedersen J. Schleicher and S. Shumarayev \"PLD Routing Architecture with Both Fast and Regular Routing Resources\" US Patent Application Pending."},{"key":"e_1_3_2_1_10_2","doi-asserted-by":"publisher","DOI":"10.1145\/368640.368816"},{"key":"e_1_3_2_1_11_2","doi-asserted-by":"publisher","DOI":"10.1145\/360276.360286"},{"key":"e_1_3_2_1_12_2","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296405"},{"key":"e_1_3_2_1_13_2","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296426"},{"key":"e_1_3_2_1_14_2","unstructured":"T. Ngai B. Pedersen S. Shumarayev J. Schleicher W-J. Huang M. Hutton V. Maruri R. Patel P. Kazarian A. Leaver D. Mendel and J. Park. \"Interconnection and Input\/Output Resources for Programmable Logic Integrated Circuit Devices\" US Patent Applicatoin Pending.  T. Ngai B. Pedersen S. Shumarayev J. Schleicher W-J. Huang M. Hutton V. Maruri R. Patel P. Kazarian A. Leaver D. Mendel and J. Park. \"Interconnection and Input\/Output Resources for Programmable Logic Integrated Circuit Devices\" US Patent Applicatoin Pending."},{"key":"e_1_3_2_1_15_2","doi-asserted-by":"publisher","DOI":"10.1145\/275107.275111"},{"key":"e_1_3_2_1_16_2","unstructured":"J. Park B. Pedersen and W-J. Huang \"Carry-lookahead\" US Patent Application Pending.  J. Park B. Pedersen and W-J. Huang \"Carry-lookahead\" US Patent Application Pending."},{"key":"e_1_3_2_1_17_2","unstructured":"B. Pedersen and J. Park \"Dedicated Multiplier\" US Patent Application Pending.  B. Pedersen and J. Park \"Dedicated Multiplier\" US Patent Application Pending."},{"key":"e_1_3_2_1_18_2","author":"Rose J.","year":"1990","unstructured":"J. Rose , R.J. Francis , D. Lewis and P. Chow . \"Architecture of Field-Programmable Gate Arrays: The Effect of Logic Block Functionality on Area Efficiency,\" In. IEEE J. Solid-State Circuits , 1990 . J. Rose, R.J. Francis, D. Lewis and P. Chow. \"Architecture of Field-Programmable Gate Arrays: The Effect of Logic Block Functionality on Area Efficiency,\" In. IEEE J. Solid-State Circuits, 1990.","journal-title":"IEEE J. Solid-State Circuits"},{"key":"e_1_3_2_1_19_2","unstructured":"J. Schleicher and M. Hutton. \"Fast Cascade\". US Patent Application Pending.  J. Schleicher and M. Hutton. \"Fast Cascade\". US Patent Application Pending."},{"key":"e_1_3_2_1_20_2","doi-asserted-by":"publisher","DOI":"10.1145\/258305.258306"},{"key":"e_1_3_2_1_21_2","doi-asserted-by":"publisher","DOI":"10.1145\/275107.275115"},{"key":"e_1_3_2_1_22_2","unstructured":"Xilinx Corp. http:\/\/www.xilinx.com.  Xilinx Corp. http:\/\/www.xilinx.com."}],"event":{"name":"FPGA02: ACM\/SIGDA International Symposium on Field Programmable Gate Arrays","sponsor":["SIGDA ACM Special Interest Group on Design Automation"],"location":"Monterey California USA","acronym":"FPGA02"},"container-title":["Proceedings of the 2002 ACM\/SIGDA tenth international symposium on Field-programmable gate arrays"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/503048.503050","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/503048.503050","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T17:24:26Z","timestamp":1750267466000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/503048.503050"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2002,2,24]]},"references-count":22,"alternative-id":["10.1145\/503048.503050","10.1145\/503048"],"URL":"https:\/\/doi.org\/10.1145\/503048.503050","relation":{},"subject":[],"published":{"date-parts":[[2002,2,24]]},"assertion":[{"value":"2002-02-24","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}