{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:35:17Z","timestamp":1750307717848,"version":"3.41.0"},"reference-count":21,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2009,5,1]],"date-time":"2009-05-01T00:00:00Z","timestamp":1241136000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100001871","name":"Funda\u00e7\u00e3o para a Ci\u00eancia e a Tecnologia","doi-asserted-by":"publisher","award":["EEA-ESE\/61528\/2004"],"award-info":[{"award-number":["EEA-ESE\/61528\/2004"]}],"id":[{"id":"10.13039\/501100001871","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2009,5]]},"abstract":"<jats:p>Power analysis tools are an integral component of any current power sign-off methodology. The performance of a design's power grid affects the timing and functionality of a circuit, directly impacting the overall performance. Ensuring power grid robustness implies taking into account, among others, static and dynamic effects of voltage drop, ground bounce, and electromigration. This type of verification is usually done by simulation, targeting a worst-case scenario where devices, switching almost simultaneously, could impose stern current demands on the power grid. While determination of the exact worst-case switching conditions from the grid perspective is usually not practical, the choice of simulation stimuli has a critical effect on the results of the analysis. Targetting safe but unrealistic settings could lead to pessimistic results and costly overdesigns in terms of die area. In this article we describe a software tool that generates a reasonable, realistic, set of stimuli for simulation. The approach proposed accounts for timing and spatial restrictions that arise from the circuit's netlist and placement and generates an approximation to the worst-case condition. The resulting stimuli indicate that only a fraction of the gates change in any given timing window, leading to a more robust verification methodology, especially in the dynamic case. Generating such stimuli is akin to performing a standard static timing analysis, so the tool fits well within conventional design frameworks. Furthermore, the tool can be used for hotspot detection in early design stages.<\/jats:p>","DOI":"10.1145\/1529255.1529262","type":"journal-article","created":{"date-parts":[[2009,6,2]],"date-time":"2009-06-02T14:51:08Z","timestamp":1243954268000},"page":"1-26","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":7,"title":["Generating realistic stimuli for accurate power grid analysis"],"prefix":"10.1145","volume":"14","author":[{"given":"P. Marques","family":"Morgado","sequence":"first","affiliation":[{"name":"INESC ID\/IST - TU Lisbon, Lisboa, Portugal"}]},{"given":"Paulo F.","family":"Flores","sequence":"additional","affiliation":[{"name":"INESC ID\/IST - TU Lisbon, Lisboa, Portugal"}]},{"given":"L. Miguel","family":"Silveira","sequence":"additional","affiliation":[{"name":"INESC ID\/Cadence Research Laboratories\/IST - TU Lisbon, Lisboa, Portugal"}]}],"member":"320","published-online":{"date-parts":[[2009,6,4]]},"reference":[{"volume-title":"Cadence Design Systems","author":"Cadence","key":"e_1_2_1_1_1","unstructured":"Cadence . 2001. Power grid verification. Whitepaper , Cadence Design Systems , Inc . Cadence. 2001. Power grid verification. Whitepaper, Cadence Design Systems, Inc."},{"volume-title":"Proceedings of the Asian and South-Pacific Design Automation Conference (ASP-DAC). ACM\/IEEE, 65--70","author":"Choi S. H.","key":"e_1_2_1_2_1","unstructured":"Choi , S. H. , Paul , B. C. , and Roy , K . 2002. Dynamic noise analysis with capacitive and inductive coupling . In Proceedings of the Asian and South-Pacific Design Automation Conference (ASP-DAC). ACM\/IEEE, 65--70 . Choi, S. H., Paul, B. C., and Roy, K. 2002. Dynamic noise analysis with capacitive and inductive coupling. In Proceedings of the Asian and South-Pacific Design Automation Conference (ASP-DAC). ACM\/IEEE, 65--70."},{"volume-title":"Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design (ICCAD). IEEE Computer Society, 770--777","author":"Ferzli I. A.","key":"e_1_2_1_3_1","unstructured":"Ferzli , I. A. and Najm , F. N . 2003a. Statistical verification of power grids considering process-induced leakage current variations . In Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design (ICCAD). IEEE Computer Society, 770--777 . Ferzli, I. A. and Najm, F. N. 2003a. Statistical verification of power grids considering process-induced leakage current variations. In Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design (ICCAD). IEEE Computer Society, 770--777."},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/775832.776047"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1283780.1283805"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2007.61"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.282"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775861"},{"volume-title":"Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design (ICCAD). ACM\/IEEE, 358--364","author":"Kouroussis D.","key":"e_1_2_1_9_1","unstructured":"Kouroussis , D. and Najm , I. A. F. F. N. 2005. Incremental partitioning-based vectorless power grid verification . In Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design (ICCAD). ACM\/IEEE, 358--364 . Kouroussis, D. and Najm, I. A. F. F. N. 2005. Incremental partitioning-based vectorless power grid verification. In Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design (ICCAD). ACM\/IEEE, 358--364."},{"key":"e_1_2_1_10_1","volume-title":"Proceedings of the IEEE International Conference on Computer Design on VLSI in Computer and Processors (ICCD '91)","author":"Krodel T. H.","year":"1991","unstructured":"Krodel , T. H. 1991 . Powerplay-Fast dynamic power estimation based on logic simulation . In Proceedings of the IEEE International Conference on Computer Design on VLSI in Computer and Processors (ICCD '91) . IEEE Computer Society, 96--100. Krodel, T. H. 1991. Powerplay-Fast dynamic power estimation based on logic simulation. In Proceedings of the IEEE International Conference on Computer Design on VLSI in Computer and Processors (ICCD '91). IEEE Computer Society, 96--100."},{"volume-title":"Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design (ICCAD). ACM\/IEEE, 651--654","author":"Lin S.","key":"e_1_2_1_11_1","unstructured":"Lin , S. and Chang , N . 2001. Challenges in power-ground integrity . In Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design (ICCAD). ACM\/IEEE, 651--654 . Lin, S. and Chang, N. 2001. Challenges in power-ground integrity. In Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design (ICCAD). ACM\/IEEE, 651--654."},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379043"},{"volume-title":"Proceedings of the Design, Automation and Test in Europe Conference (DATE). IEEE, 1538--1543","author":"Mangassarian H.","key":"e_1_2_1_13_1","unstructured":"Mangassarian , H. , Veneris , A. , Safarpour , S. , Najm , F. N. , and Abadir , M. S . 2007. Maximum circuit activity estimation using pseudo-boolean satisfiability . In Proceedings of the Design, Automation and Test in Europe Conference (DATE). IEEE, 1538--1543 . Mangassarian, H., Veneris, A., Safarpour, S., Najm, F. N., and Abadir, M. S. 2007. Maximum circuit activity estimation using pseudo-boolean satisfiability. In Proceedings of the Design, Automation and Test in Europe Conference (DATE). IEEE, 1538--1543."},{"key":"e_1_2_1_14_1","doi-asserted-by":"crossref","unstructured":"Morgado P. M. Flores P. F. Monteiro J. C. and Silveira L. M. 2008. Generating worst case stimuli for accurate power grid analysis. In Proceedings of the PATMOS Workshop (to be published by Springer in Lecture Notes for Computer Science). Springer-Verlag.  Morgado P. M. Flores P. F. Monteiro J. C. and Silveira L. M. 2008. Generating worst case stimuli for accurate power grid analysis. In Proceedings of the PATMOS Workshop (to be published by Springer in Lecture Notes for Computer Science). Springer-Verlag.","DOI":"10.1007\/978-3-540-95948-9_25"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065781"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/337292.337359"},{"volume-title":"Proceedings of the International Solid-State Circuits Conference Technical Papers (ISSCC). IEEE, 226--227","author":"Sato T.","key":"e_1_2_1_17_1","unstructured":"Sato , T. , Sylvester , D. , Cao , Y. , and Hu , C . 2000. Accurate in-situ measurement of peak noise and signal delay induced by interconnect coupling . In Proceedings of the International Solid-State Circuits Conference Technical Papers (ISSCC). IEEE, 226--227 . Sato, T., Sylvester, D., Cao, Y., and Hu, C. 2000. Accurate in-situ measurement of peak noise and signal delay induced by interconnect coupling. In Proceedings of the International Solid-State Circuits Conference Technical Papers (ISSCC). IEEE, 226--227."},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.809658"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996663"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/1055137.1055156"},{"volume-title":"Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design (ICCAD '05)","author":"Zhong Y.","key":"e_1_2_1_21_1","unstructured":"Zhong , Y. and Wong , M. D. F. 2005. Fast algorithms for ir drop analysis in large power grid . In Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design (ICCAD '05) . IEEE Computer Society, 351--357. Zhong, Y. and Wong, M. D. F. 2005. Fast algorithms for ir drop analysis in large power grid. In Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design (ICCAD '05). IEEE Computer Society, 351--357."}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1529255.1529262","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1529255.1529262","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T13:30:26Z","timestamp":1750253426000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1529255.1529262"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,5]]},"references-count":21,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2009,5]]}},"alternative-id":["10.1145\/1529255.1529262"],"URL":"https:\/\/doi.org\/10.1145\/1529255.1529262","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"type":"print","value":"1084-4309"},{"type":"electronic","value":"1557-7309"}],"subject":[],"published":{"date-parts":[[2009,5]]},"assertion":[{"value":"2007-09-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2009-03-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2009-06-04","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}