{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,22]],"date-time":"2025-11-22T10:56:01Z","timestamp":1763808961592,"version":"3.41.0"},"reference-count":216,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2010,6,1]],"date-time":"2010-06-01T00:00:00Z","timestamp":1275350400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100001871","name":"Funda\u00e7\u00e3o para a Ci\u00eancia e a Tecnologia","doi-asserted-by":"publisher","award":["PTDC\/EEA-ELC\/71556\/2006PTDC\/EEA-ELC\/70272\/2006POSI\/CHS\/48018\/2002"],"award-info":[{"award-number":["PTDC\/EEA-ELC\/71556\/2006PTDC\/EEA-ELC\/70272\/2006POSI\/CHS\/48018\/2002"]}],"id":[{"id":"10.13039\/501100001871","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Comput. Surv."],"published-print":{"date-parts":[[2010,6]]},"abstract":"<jats:p>Reconfigurable computing platforms offer the promise of substantially accelerating computations through the concurrent nature of hardware structures and the ability of these architectures for hardware customization. Effectively programming such reconfigurable architectures, however, is an extremely cumbersome and error-prone process, as it requires programmers to assume the role of hardware designers while mastering hardware description languages, thus limiting the acceptance and dissemination of this promising technology. To address this problem, researchers have developed numerous approaches at both the programming languages as well as the compilation levels, to offer high-level programming abstractions that would allow programmers to easily map applications to reconfigurable architectures. This survey describes the major research efforts on compilation techniques for reconfigurable computing architectures. The survey focuses on efforts that map computations written in imperative programming languages to reconfigurable architectures and identifies the main compilation and synthesis techniques used in this mapping.<\/jats:p>","DOI":"10.1145\/1749603.1749604","type":"journal-article","created":{"date-parts":[[2010,6,22]],"date-time":"2010-06-22T12:20:45Z","timestamp":1277209245000},"page":"1-65","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":78,"title":["Compiling for reconfigurable computing"],"prefix":"10.1145","volume":"42","author":[{"given":"Jo\u00e3o M. P.","family":"Cardoso","sequence":"first","affiliation":[{"name":"Universidade do Porto, Porto, Portugal"}]},{"given":"Pedro C.","family":"Diniz","sequence":"additional","affiliation":[{"name":"Instituto Superior T\u00e9cnico and INESC-ID, Lisboa, Portugal"}]},{"given":"Markus","family":"Weinhardt","sequence":"additional","affiliation":[{"name":"Fachhochschule Osnabr\u00fcck, Osnabr\u00fcck, Germany"}]}],"member":"320","published-online":{"date-parts":[[2010,6,23]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/354880.354899"},{"key":"e_1_2_1_2_1","unstructured":"Accelchip. http:\/\/www.accelchip.com\/.  Accelchip. http:\/\/www.accelchip.com\/."},{"volume-title":"Proceedings of the 2nd IEEE Workshop on FPGAs for Custom Computing Machines (FCCM'94)","author":"Agarwal L.","key":"e_1_2_1_3_1","unstructured":"Agarwal , L. , Wazlowski , M. , and Ghosh , S . 1994. An asynchronous approach to efficient execution of programs on adaptive architectures utilizing FPGAs . In Proceedings of the 2nd IEEE Workshop on FPGAs for Custom Computing Machines (FCCM'94) . IEEE, Los Alamitos, CA, 101--110. Agarwal, L., Wazlowski, M., and Ghosh, S. 1994. An asynchronous approach to efficient execution of programs on adaptive architectures utilizing FPGAs. In Proceedings of the 2nd IEEE Workshop on FPGAs for Custom Computing Machines (FCCM'94). IEEE, Los Alamitos, CA, 101--110."},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/567067.567085"},{"key":"e_1_2_1_5_1","unstructured":"Altera Inc. http:\/\/www.altera.com\/.  Altera Inc. http:\/\/www.altera.com\/."},{"volume-title":"Stratix programmable logic device family data sheet 1.0","author":"Altera Inc. 2002.","key":"e_1_2_1_6_1","unstructured":"Altera Inc. 2002. Stratix programmable logic device family data sheet 1.0 , H.W.A.C. Altera Corp . Altera Inc. 2002. Stratix programmable logic device family data sheet 1.0, H.W.A.C. Altera Corp."},{"volume-title":"Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines (FCCM'95)","author":"Amerson R.","key":"e_1_2_1_7_1","unstructured":"Amerson , R. , Carter , R. J. , Culbertson , W. B. , Kuekes , P. , and Snider , G . 1995. Teramac-configurable custom computing . In Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines (FCCM'95) . IEEE, Los Alamitos, CA, 32--38. Amerson, R., Carter, R. J., Culbertson, W. B., Kuekes, P., and Snider, G. 1995. Teramac-configurable custom computing. In Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines (FCCM'95). IEEE, Los Alamitos, CA, 32--38."},{"key":"e_1_2_1_8_1","unstructured":"Annapolis Microsystems Inc. 1999. WildStarTM reconfigurable computing engines User's manual R3.3.  Annapolis Microsystems Inc. 1999. WildStarTM reconfigurable computing engines User's manual R3.3."},{"volume-title":"An Adaptive Machine Architecture and Compiler for Dynamic Processor Reconfiguration","author":"Athanas P.","key":"e_1_2_1_9_1","unstructured":"Athanas , P. 1992. An Adaptive Machine Architecture and Compiler for Dynamic Processor Reconfiguration . Brown University . Athanas, P. 1992. An Adaptive Machine Architecture and Compiler for Dynamic Processor Reconfiguration. Brown University."},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.204677"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/300979.300997"},{"volume-title":"Proceedings of the 7th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'99)","author":"Babb J.","key":"e_1_2_1_13_1","unstructured":"Babb , J. , Rinard , M. , Moritz , C. A. , Lee , W. , Frank , M. , Barua , R. , and Amarasinghe , S . 1999. Parallelizing applications into silicon . In Proceedings of the 7th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'99) . IEEE, Los Alamitos, CA, 70--81. Babb, J., Rinard, M., Moritz, C. A., Lee, W., Frank, M., Barua, R., and Amarasinghe, S. 1999. Parallelizing applications into silicon. In Proceedings of the 7th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'99). IEEE, Los Alamitos, CA, 70--81."},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.5555\/795659.795917"},{"volume-title":"Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'06)","author":"Baradaran N.","key":"e_1_2_1_15_1","unstructured":"Baradaran , N. and Diniz , P . 2006. Memory parallelism using custom array mapping to heterogeneous storage structures . In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'06) . IEEE, Los Alamitos, CA, 383--388. Baradaran, N. and Diniz, P. 2006. Memory parallelism using custom array mapping to heterogeneous storage structures. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'06). IEEE, Los Alamitos, CA, 383--388."},{"volume-title":"Proceedings of the IEEE International Conference on Field-Programmable Technology (FPT'04)","author":"Baradaran N.","key":"e_1_2_1_16_1","unstructured":"Baradaran , N. , Park , J. , and Diniz , P . 2004. Compiler reuse analysis for the mapping of data in FPGAs with RAM blocks . In Proceedings of the IEEE International Conference on Field-Programmable Technology (FPT'04) . IEEE, Los Alamitos, CA, 45--152. Baradaran, N., Park, J., and Diniz, P. 2004. Compiler reuse analysis for the mapping of data in FPGAs with RAM blocks. In Proceedings of the IEEE International Conference on Field-Programmable Technology (FPT'04). IEEE, Los Alamitos, CA, 45--152."},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.966497"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1023\/A:1024499601571"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1007\/BF01205183"},{"volume-title":"Proceedings of the Asia South Pacific Design Automation Conference (ASP-DAC'98)","author":"Becker J.","key":"e_1_2_1_20_1","unstructured":"Becker , J. , Hartenstein , R. , Herz , M. , and Nageldinger , U . 1998. Parallelization in co-compilation for configurable accelerators . In Proceedings of the Asia South Pacific Design Automation Conference (ASP-DAC'98) , 23--33. Becker, J., Hartenstein, R., Herz, M., and Nageldinger, U. 1998. Parallelization in co-compilation for configurable accelerators. In Proceedings of the Asia South Pacific Design Automation Conference (ASP-DAC'98), 23--33."},{"volume-title":"Proceedings of the IEEE 6th Symposium on Field-Programmable Custom Computing Machines (FCCM'98)","author":"Bellows P.","key":"e_1_2_1_21_1","unstructured":"Bellows , P. and Hutchings , B . 1998. JHDL-An HDL for reconfigurable systems . In Proceedings of the IEEE 6th Symposium on Field-Programmable Custom Computing Machines (FCCM'98) . IEEE, Los Alamitos, CA, 175--184. Bellows, P. and Hutchings, B. 1998. JHDL-An HDL for reconfigurable systems. In Proceedings of the IEEE 6th Symposium on Field-Programmable Custom Computing Machines (FCCM'98). IEEE, Los Alamitos, CA, 175--184."},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1002\/spe.4380160704"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/289423.289440"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1023\/A:1013623303037"},{"volume-title":"Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01)","author":"B\u00f6hm A. P. W.","key":"e_1_2_1_25_1","unstructured":"B\u00f6hm , A. P. W. , Draper , B. , Najjar , W. , Hammes , J. , Rinker , R. , Chawathe , M. , and Ross , C . 2001. One-step compilation of image processing algorithms to FPGAs . In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01) . IEEE, Los Alamitos, CA, 209--218. B\u00f6hm, A. P. W., Draper, B., Najjar, W., Hammes, J., Rinker, R., Chawathe, M., and Ross, C. 2001. One-step compilation of image processing algorithms to FPGAs. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01). IEEE, Los Alamitos, CA, 209--218."},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/378239.378483"},{"key":"e_1_2_1_27_1","series-title":"Lecture Notes in Computer Science","volume-title":"DEFACTO: A design environment for adaptive computing technology. In Proceedings of the 6th Reconfigurable Architectures Workshop (RAW'99)","author":"Bondalapati K.","year":"1999","unstructured":"Bondalapati , K. , Diniz , P. , Duncan , P. , Granacki , J. , Hall , M. , Jain , R. , and Ziegler , H . 1999 . DEFACTO: A design environment for adaptive computing technology. In Proceedings of the 6th Reconfigurable Architectures Workshop (RAW'99) . Lecture Notes in Computer Science , vol. 1586 , Springer , Berlin , 570--578. Bondalapati, K., Diniz, P., Duncan, P., Granacki, J., Hall, M., Jain, R., and Ziegler, H. 1999. DEFACTO: A design environment for adaptive computing technology. In Proceedings of the 6th Reconfigurable Architectures Workshop (RAW'99). Lecture Notes in Computer Science, vol. 1586, Springer, Berlin, 570--578."},{"volume-title":"Proceedings of the 7th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'99)","author":"Bondalapati K.","key":"e_1_2_1_28_1","unstructured":"Bondalapati , K. and Prasanna , V. K . 1999. Dynamic precision management for loop computations on reconfigurable architectures . In Proceedings of the 7th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'99) . IEEE, Los Alamitos, CA, 249--258. Bondalapati, K. and Prasanna, V. K. 1999. Dynamic precision management for loop computations on reconfigurable architectures. In Proceedings of the 7th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'99). IEEE, Los Alamitos, CA, 249--258."},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.709397"},{"volume-title":"Proceedings of the 5th International Symposium on High Performance Computer Architecture (HPCA'99)","author":"Brooks D.","key":"e_1_2_1_30_1","unstructured":"Brooks , D. and Martonosi , M . 1999. Dynamically exploiting narrow width operands to improve processor power and performance . In Proceedings of the 5th International Symposium on High Performance Computer Architecture (HPCA'99) . IEEE, Los Alamitos, CA, 13--22. Brooks, D. and Martonosi, M. 1999. Dynamically exploiting narrow width operands to improve processor power and performance. In Proceedings of the 5th International Symposium on High Performance Computer Architecture (HPCA'99). IEEE, Los Alamitos, CA, 13--22."},{"key":"e_1_2_1_31_1","volume-title":"Proceedings of the 6th International European Conference on Parallel Computing (EuroPar'00)","volume":"1900","author":"Budiu M.","unstructured":"Budiu , M. , Goldstein , S. , Sakr , M. , and Walker , K . 2000. BitValue inference: Detecting and exploiting narrow bit-width computations . In Proceedings of the 6th International European Conference on Parallel Computing (EuroPar'00) . Lecture Notes in Computer Science , vol. 1900 , Springer, Berlin, 969--979. Budiu, M., Goldstein, S., Sakr, M., and Walker, K. 2000. BitValue inference: Detecting and exploiting narrow bit-width computations. In Proceedings of the 6th International European Conference on Parallel Computing (EuroPar'00). Lecture Notes in Computer Science, vol. 1900, Springer, Berlin, 969--979."},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296459"},{"volume-title":"Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers &amp; Processors (ICCD'00)","author":"Cadambi S.","key":"e_1_2_1_33_1","unstructured":"Cadambi , S. and Goldstein , S . 2000. Efficient place and route for pipeline reconfigurable architectures . In Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers &amp; Processors (ICCD'00) . IEEE, Los Alamitos, CA, 423--429. Cadambi, S. and Goldstein, S. 2000. Efficient place and route for pipeline reconfigurable architectures. In Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers &amp; Processors (ICCD'00). IEEE, Los Alamitos, CA, 423--429."},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.839323"},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/354880.354889"},{"key":"e_1_2_1_37_1","volume-title":"Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications (FPL'98)","volume":"1482","author":"Callahan T. J.","unstructured":"Callahan , T. J. and Wawrzynek , J . 1998. Instruction-level parallelism for reconfigurable computing . In Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications (FPL'98) . Lecture Notes in Computer Science , vol. 1482 , Springer, Berlin, 248--257. Callahan, T. J. and Wawrzynek, J. 1998. Instruction-level parallelism for reconfigurable computing. In Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications (FPL'98). Lecture Notes in Computer Science, vol. 1482, Springer, Berlin, 248--257."},{"key":"e_1_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/275107.275132"},{"key":"e_1_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2003.1234532"},{"key":"e_1_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2003.1188264"},{"volume-title":"Proceedings of the 12th International Conference on Field-Programmable Logic and Applications (FPL'02)","author":"Cardoso J. M. P.","key":"e_1_2_1_41_1","unstructured":"Cardoso , J. M. P. and Weinhardt , M . 2002. XPP-VC: A C compiler with temporal partitioning for the PACT-XPP architecture . In Proceedings of the 12th International Conference on Field-Programmable Logic and Applications (FPL'02) . Lecture Notes in Computer Science, Springer, Berlin, 864--874. Cardoso, J. M. P. and Weinhardt, M. 2002. XPP-VC: A C compiler with temporal partitioning for the PACT-XPP architecture. In Proceedings of the 12th International Conference on Field-Programmable Logic and Applications (FPL'02). Lecture Notes in Computer Science, Springer, Berlin, 864--874."},{"key":"e_1_2_1_42_1","volume-title":"Proceedings of the 11th International Conference on Field Programmable Logic and Applications (FPL'01)","volume":"2147","author":"Cardoso J. M. P.","unstructured":"Cardoso , J. M. P. and Neto , H. C . 2001. Compilation increasing the scheduling scope for multi-memory-FPGA-based custom computing machines . In Proceedings of the 11th International Conference on Field Programmable Logic and Applications (FPL'01) . Lecture Notes in Computer Science , vol. 2147 , Springer, Berlin, 523--533. Cardoso, J. M. P. and Neto, H. C. 2001. Compilation increasing the scheduling scope for multi-memory-FPGA-based custom computing machines. In Proceedings of the 11th International Conference on Field Programmable Logic and Applications (FPL'01). Lecture Notes in Computer Science, vol. 2147, Springer, Berlin, 523--533."},{"volume-title":"Proceedings of the IFIP TC10\/WG10","author":"Cardoso J. M. P.","key":"e_1_2_1_43_1","unstructured":"Cardoso , J. M. P. and Neto , H. C . 2000. An enhanced static-list scheduling algorithm for temporal partitioning onto RPUs . In Proceedings of the IFIP TC10\/WG10 .5 10th International Conference on Very Large Scale Integration (VLSI'99). Cardoso, J. M. P. and Neto, H. C. 2000. An enhanced static-list scheduling algorithm for temporal partitioning onto RPUs. In Proceedings of the IFIP TC10\/WG10.5 10th International Conference on Very Large Scale Integration (VLSI'99)."},{"volume-title":"Proceedings of the IEEE 7th Symposium on Field-Programmable Custom Computing Machines (FCCM'99)","author":"Cardoso J. M. P.","key":"e_1_2_1_44_1","unstructured":"Cardoso , J. M. P. and Neto , H. C . 1999. Macro-based hardware compilation of Java bytecodes into a dynamic reconfigurable computing system . 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IEEE, Los Alamitos, CA, 106--115."},{"key":"e_1_2_1_59_1","volume-title":"Proceedings of the 6th International Workshop on Field-Programmable Logic and Applications (FPL'95)","volume":"975","author":"Ebeling C.","unstructured":"Ebeling , C. , Cronquist , D. C. , and Franklin , P . 1995. RaPiD\u2014Reconfigurable pipelined datapath . In Proceedings of the 6th International Workshop on Field-Programmable Logic and Applications (FPL'95) . Lecture Notes in Computer Science , vol. 975 , Springer, Berlin, 126--135. Ebeling, C., Cronquist, D. C., and Franklin, P. 1995. RaPiD\u2014Reconfigurable pipelined datapath. In Proceedings of the 6th International Workshop on Field-Programmable Logic and Applications (FPL'95). Lecture Notes in Computer Science, vol. 975, Springer, Berlin, 126--135."},{"key":"e_1_2_1_60_1","volume-title":"Proceedings of the 11th IEEE\/ACM International Workshop on Logic and Synthesis (IWLS'02)","author":"Edwards S.","year":"2002","unstructured":"Edwards , S. 2002 . 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Reconfigurable Computing: Accelerating Computation with Field-Programmable Gate Arrays . Springer , Berlin . Gokhale, M. and Graham, P. S. 2005. Reconfigurable Computing: Accelerating Computation with Field-Programmable Gate Arrays. Springer, Berlin."},{"key":"e_1_2_1_70_1","doi-asserted-by":"publisher","DOI":"10.5555\/344169.2813228"},{"key":"e_1_2_1_71_1","doi-asserted-by":"publisher","DOI":"10.5555\/795659.795916"},{"volume-title":"Proceedings of the 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'99)","author":"Gokhale M.","key":"e_1_2_1_72_1","unstructured":"Gokhale , M. and Stone , J . 1999. Automatic allocation of arrays to memories in FPGA processors with multiple memory banks . In Proceedings of the 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'99) . IEEE, Los Alamitos, CA, 63--69. Gokhale, M. and Stone, J. 1999. Automatic allocation of arrays to memories in FPGA processors with multiple memory banks. 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IEEE, Los Alamitos, CA, 314--319."},{"volume-title":"Proceedings of the 14th International Conference on VLSI Design (VLSID'01)","author":"Haldar M.","key":"e_1_2_1_86_1","unstructured":"Haldar , M. , Nayak , A. , Shenoy , N. , Choudhary , A. , and Banerjee , P . 2001b. FPGA hardware synthesis from MATLAB . In Proceedings of the 14th International Conference on VLSI Design (VLSID'01) . 299--304. Haldar, M., Nayak, A., Shenoy, N., Choudhary, A., and Banerjee, P. 2001b. FPGA hardware synthesis from MATLAB. In Proceedings of the 14th International Conference on VLSI Design (VLSID'01). 299--304."},{"key":"e_1_2_1_87_1","doi-asserted-by":"publisher","DOI":"10.5555\/367072.367839"},{"key":"e_1_2_1_88_1","volume-title":"Proceedings of the International Conference on Innovative Systems in Silicon (ISIS'97)","author":"Hartenstein R. W.","year":"1997","unstructured":"Hartenstein , R. W. 1997 . The microprocessor is no more general purpose: Why future reconfigurable platforms will win . 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Exper. 8 6 429--443.","DOI":"10.1002\/(SICI)1096-9128(199607)8:6<429::AID-CPE252>3.0.CO;2-9"},{"key":"e_1_2_1_90_1","doi-asserted-by":"publisher","DOI":"10.1145\/224818.224959"},{"key":"e_1_2_1_91_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1991.176054"},{"key":"e_1_2_1_92_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.821545"},{"key":"e_1_2_1_93_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.663540"},{"volume-title":"Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines (FCCM'97)","author":"Hauser J. R.","key":"e_1_2_1_94_1","unstructured":"Hauser , J. R. and Wawrzynek , J . 1997. Garp: A MIPS processor with a reconfigurable coprocessor . In Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines (FCCM'97) . IEEE, Los Alamitos, CA, 12--21. Hauser, J. R. and Wawrzynek, J. 1997. Garp: A MIPS processor with a reconfigurable coprocessor. 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S.","key":"e_1_2_1_106_1","unstructured":"Khouri , K. S. , Lakshminarayana , G. , and Jha , N. K . 1999. Memory binding for performance optimization of control-flow intensive behaviors . In Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design (ICCAD'99) . IEEE, Los Alamitos, CA, 482--488. Khouri, K. S., Lakshminarayana, G., and Jha, N. K. 1999. Memory binding for performance optimization of control-flow intensive behaviors. In Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design (ICCAD'99). IEEE, Los Alamitos, CA, 482--488."},{"volume-title":"DSP. In Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP'04)","author":"Kobayashi S.","key":"e_1_2_1_107_1","unstructured":"Kobayashi , S. , Kozuka , I. , Tang , W. H. , and Landmann , D. 2004. A software\/hardware codesigned hands-free system on a \u201cresizable\u201d block-floating-point DSP. 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IEEE, Los Alamitos, CA, 166--173."},{"key":"e_1_2_1_129_1","volume-title":"Proceedings of the International Conference on Field Programmable Logic and Application (FPL'03)","volume":"2778","author":"Mei B.","unstructured":"Mei , B. , Vernalde , S. , Verkest , D. , Man , H. D. , and Lauwereins , R . 2003. ADRES: An architecture with tightly coupled VLIW processor and coarse-grained reconfigurable matrix . In Proceedings of the International Conference on Field Programmable Logic and Application (FPL'03) . Lecture Notes in Computer Science , vol. 2778 , Springer, Berlin, 61--70. Mei, B., Vernalde, S., Verkest, D., Man, H. D., and Lauwereins, R. 2003. ADRES: An architecture with tightly coupled VLIW processor and coarse-grained reconfigurable matrix. In Proceedings of the International Conference on Field Programmable Logic and Application (FPL'03). Lecture Notes in Computer Science, vol. 2778, Springer, Berlin, 61--70."},{"key":"e_1_2_1_130_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.920835"},{"volume-title":"Synthesis and Optimization of Digital Circuits","author":"Micheli G. D.","key":"e_1_2_1_131_1","unstructured":"Micheli , G. D. 1994. Synthesis and Optimization of Digital Circuits . McGraw Hill , New York . Micheli, G. D. 1994. Synthesis and Optimization of Digital Circuits. McGraw Hill, New York."},{"key":"e_1_2_1_132_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.558708"},{"volume-title":"Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines (FCCM'96)","author":"Mirsky E.","key":"e_1_2_1_133_1","unstructured":"Mirsky , E. and Dehon , A . 1996. MATRIX: A reconfigurable computing device with reconfigurable instruction deployable resources . In Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines (FCCM'96) . IEEE, Los Alamitos, CA, 157--166. Mirsky, E. and Dehon, A. 1996. MATRIX: A reconfigurable computing device with reconfigurable instruction deployable resources. In Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines (FCCM'96). IEEE, Los Alamitos, CA, 157--166."},{"key":"e_1_2_1_134_1","unstructured":"Mitrionics A. B. http:\/\/www.mitrionics.com\/.  Mitrionics A. B. http:\/\/www.mitrionics.com\/."},{"volume-title":"Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines (FCCM'98)","author":"Miyamori T.","key":"e_1_2_1_135_1","unstructured":"Miyamori , T. and Olukotun , K . 1998. A quantitative analysis of reconfigurable coprocessors for multimedia applications . In Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines (FCCM'98) . IEEE, Los Alamitos, CA, 2--11. Miyamori, T. and Olukotun, K. 1998. A quantitative analysis of reconfigurable coprocessors for multimedia applications. In Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines (FCCM'98). IEEE, Los Alamitos, CA, 2--11."},{"key":"e_1_2_1_136_1","doi-asserted-by":"publisher","DOI":"10.1145\/201310.201318"},{"volume-title":"Advanced Compiler Design and Implementation. Morgan Kaufmann","author":"Muchnick S. S.","key":"e_1_2_1_137_1","unstructured":"Muchnick , S. S. 1997. Advanced Compiler Design and Implementation. Morgan Kaufmann , San Francisco, CA . Muchnick, S. S. 1997. Advanced Compiler Design and Implementation. Morgan Kaufmann, San Francisco, CA."},{"key":"e_1_2_1_138_1","unstructured":"Nallatech Inc. http:\/\/www.nallatech.com.  Nallatech Inc. http:\/\/www.nallatech.com."},{"volume-title":"Proceedings of the IEEE 9th Symposium on Field-Programmable Custom Computing Machines (FCCM'01)","author":"Nayak A.","key":"e_1_2_1_139_1","unstructured":"Nayak , A. , Haldar , M. , Choudhary , A. , and Banerjee , P . 2001a. Parallelization of Matlab applications for a multi-FPGA system . In Proceedings of the IEEE 9th Symposium on Field-Programmable Custom Computing Machines (FCCM'01) . IEEE, Los Alamitos, CA, 1--9. Nayak, A., Haldar, M., Choudhary, A., and Banerjee, P. 2001a. Parallelization of Matlab applications for a multi-FPGA system. In Proceedings of the IEEE 9th Symposium on Field-Programmable Custom Computing Machines (FCCM'01). IEEE, Los Alamitos, CA, 1--9."},{"volume-title":"Proceedings of the Design, Automation and Test Conference in Europe (DATE'01)","author":"Nayak A.","key":"e_1_2_1_140_1","unstructured":"Nayak , A. , Haldar , M. , Choudhary , A. , and Banerjee , P . 2001b. Precision and error analysis of MATLAB applications during automated hardware synthesis for FPGAs . In Proceedings of the Design, Automation and Test Conference in Europe (DATE'01) . IEEE, Los Alamitos, CA, 722--728. Nayak, A., Haldar, M., Choudhary, A., and Banerjee, P. 2001b. Precision and error analysis of MATLAB applications during automated hardware synthesis for FPGAs. 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Fundamentals E82-A 11 2338--2346.  Ogawa O. Takagi K. Itoh Y. Kimura S. and Watanabe K. 1999. Hardware synthesis from C programs with estimation of bit- length of variables. IEICE Trans. Fundamentals E82-A 11 2338--2346."},{"volume-title":"Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01)","author":"Ong S.-W.","key":"e_1_2_1_143_1","unstructured":"Ong , S.-W. , Kerkiz , N. , Srijanto , B. , Tan , C. , Langston , M. , Newport , D. , and Bouldin , D . 2001. Automatic mapping of multiple applications to multiple adaptive computing systems . In Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01) . IEEE, Los Alamitos, CA, 10--20. Ong, S.-W., Kerkiz, N., Srijanto, B., Tan, C., Langston, M., Newport, D., and Bouldin, D. 2001. Automatic mapping of multiple applications to multiple adaptive computing systems. In Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01). IEEE, Los Alamitos, CA, 10--20."},{"volume-title":"Proceedings of the Design, Automation and Test in Europe (DATE'01)","author":"Ouaiss I.","key":"e_1_2_1_144_1","unstructured":"Ouaiss , I. and Vemuri , R . 2001. Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers . In Proceedings of the Design, Automation and Test in Europe (DATE'01) . IEEE, Los Alamitos, CA, 650--657. Ouaiss, I. and Vemuri, R. 2001. Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers. In Proceedings of the Design, Automation and Test in Europe (DATE'01). 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VLSI Signal Process. 87--107.  Page I. 1996. Constructing hardware-software systems from a single description. J. VLSI Signal Process. 87--107.","DOI":"10.1007\/BF00936948"},{"key":"e_1_2_1_149_1","unstructured":"Page I. and Luk W. 1991. Compiling Occam into FPGAs. In FPGAs Abingdon EE&CS Books Abingdon UK 271--283.  Page I. and Luk W. 1991. Compiling Occam into FPGAs. In FPGAs Abingdon EE&CS Books Abingdon UK 271--283."},{"volume-title":"Proceedings of the SPIE Photonics East Conference. 93--103","author":"Pandey A.","key":"e_1_2_1_150_1","unstructured":"Pandey , A. and Vemuri , R . 1999. Combined temporal partitioning and scheduling for reconfigurable architectures . In Proceedings of the SPIE Photonics East Conference. 93--103 . Pandey, A. and Vemuri, R. 1999. Combined temporal partitioning and scheduling for reconfigurable architectures. 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Division of Applied Sciences","author":"Razdan R.","year":"1994","unstructured":"Razdan , R. 1994 . PRISC: Programmable reduced instruction set computers. Tech. rep. Division of Applied Sciences , Harvard University, Cambridge , MA. Razdan, R. 1994. PRISC: Programmable reduced instruction set computers. Tech. rep. Division of Applied Sciences, Harvard University, Cambridge, MA."},{"key":"e_1_2_1_163_1","doi-asserted-by":"publisher","DOI":"10.1145\/192724.192749"},{"key":"e_1_2_1_164_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.920828"},{"key":"e_1_2_1_165_1","doi-asserted-by":"publisher","DOI":"10.1145\/277650.277661"},{"volume-title":"Proceedings of the IEEE 6th Symposium on Field-Programmable Custom Computing Machines (FCCM'98)","author":"Rupp C. R.","key":"e_1_2_1_166_1","unstructured":"Rupp , C. R. , Landguth , M. , Garverick , T. , Gomersall , E. , Holt , H. , Arnold , J. M. , and Gokhale , M . 1998. The NAPA adaptive processing architecture . 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IEEE, Los Alamitos, CA, 291--302."},{"key":"e_1_2_1_179_1","volume-title":"Proceedings of the ACM Symposium on Compiler Construction (CC'04)","volume":"2985","author":"So B.","unstructured":"So , B. and Hall , M. W . 2004. Increasing the applicability of scalar replacement . In Proceedings of the ACM Symposium on Compiler Construction (CC'04) . Lecture Notes in Computer Science , vol. 2985 , Springer, Berlin,185--201. So, B. and Hall, M. W. 2004. Increasing the applicability of scalar replacement. In Proceedings of the ACM Symposium on Compiler Construction (CC'04). Lecture Notes in Computer Science, vol. 2985, Springer, Berlin,185--201."},{"key":"e_1_2_1_180_1","unstructured":"SRC Computers Inc. http:\/\/www.srccomp.com\/.  SRC Computers Inc. http:\/\/www.srccomp.com\/."},{"key":"e_1_2_1_181_1","unstructured":"Starbridge-Systems Inc. http:\/\/www.starbridgesystems.com.  Starbridge-Systems Inc. http:\/\/www.starbridgesystems.com."},{"key":"e_1_2_1_182_1","volume-title":"Proceedings of the 10th International Conference on Field-Programmable Logic and Applications (FPL'00)","volume":"1896","author":"Stefanovic D.","unstructured":"Stefanovic , D. and Martonosi , M . 2000. On availability of bit-narrow operations in general-purpose applications . In Proceedings of the 10th International Conference on Field-Programmable Logic and Applications (FPL'00) . Lecture Notes in Computer Science , vol. 1896 , Springer, Berlin, 412--421. Stefanovic, D. and Martonosi, M. 2000. On availability of bit-narrow operations in general-purpose applications. In Proceedings of the 10th International Conference on Field-Programmable Logic and Applications (FPL'00). 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Dataflow partitioning and scheduling algorithms for WASMII, a virtual hardware . In Proceedings of the 10th International Workshop on Field-Programmable Logic and Applications (FPL'00) . Lecture Notes in Computer Science , vol. 1896 , Springer, Berlin, 685--694. Takayama, A., Shibata, Y., Iwai, K., and Amano, H. 2000. Dataflow partitioning and scheduling algorithms for WASMII, a virtual hardware. In Proceedings of the 10th International Workshop on Field-Programmable Logic and Applications (FPL'00). Lecture Notes in Computer Science, vol. 1896, Springer, Berlin, 685--694."},{"key":"e_1_2_1_189_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2002.997877"},{"key":"e_1_2_1_190_1","unstructured":"Tensilica Inc. http:\/\/www.tensilica.com\/.  Tensilica Inc. http:\/\/www.tensilica.com\/."},{"key":"e_1_2_1_191_1","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008155020711"},{"key":"e_1_2_1_192_1","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:20045086"},{"key":"e_1_2_1_193_1","doi-asserted-by":"publisher","DOI":"10.1145\/275107.275135"},{"key":"e_1_2_1_194_1","series-title":"Lecture Notes in Computer Science","volume-title":"Sea Cucumber: A synthesizing compiler for FPGAs. In Proceeedings of the 12th International Conference on Field-Programmable Logic and Applications (FPL'02)","author":"Tripp J. L.","year":"2002","unstructured":"Tripp , J. L. , Jackson , P. A. , and Hutchings , B . 2002 . Sea Cucumber: A synthesizing compiler for FPGAs. In Proceeedings of the 12th International Conference on Field-Programmable Logic and Applications (FPL'02) . Lecture Notes in Computer Science , vol. 2438 , Springer , Berlin , 875--885. Tripp, J. L., Jackson, P. A., and Hutchings, B. 2002. Sea Cucumber: A synthesizing compiler for FPGAs. In Proceeedings of the 12th International Conference on Field-Programmable Logic and Applications (FPL'02). Lecture Notes in Computer Science, vol. 2438, Springer, Berlin, 875--885."},{"volume-title":"Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'05)","author":"Tripp J. L.","key":"e_1_2_1_195_1","unstructured":"Tripp , J. L. , Peterson , K. D. , Ahrens , C. , Poznanovic , J. D. , and Gokhale , M . 2005. Trident: An FPGA compiler framework for floating-point algorithms . In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'05) . IEEE, Los Alamitos, CA, 317--322. Tripp, J. L., Peterson, K. D., Ahrens, C., Poznanovic, J. D., and Gokhale, M. 2005. Trident: An FPGA compiler framework for floating-point algorithms. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'05). 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Addison-Wesley , Reading, MA . Wolfe, M. J. 1995. High Performance Compilers for Parallel Computing. Addison-Wesley, Reading, MA."},{"key":"e_1_2_1_211_1","unstructured":"Xilinx Inc. http:\/\/www.xilinx.com\/.  Xilinx Inc. http:\/\/www.xilinx.com\/."},{"key":"e_1_2_1_212_1","unstructured":"Xilinx Inc. 2001. Virtex-II 1.5V field-programmable gate arrays (v1.7). http:\/\/www.xilinx.com.  Xilinx Inc. 2001. Virtex-II 1.5V field-programmable gate arrays (v1.7). http:\/\/www.xilinx.com."},{"key":"e_1_2_1_213_1","unstructured":"XPP. XPP: The eXtreme processor platform PACT home page. http:\/\/www.pactxpp.com PACT XPP Technologies AG Munich.  XPP. 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In Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'02). IEEE, Los Alamitos, CA, 77--86."}],"container-title":["ACM Computing Surveys"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1749603.1749604","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1749603.1749604","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T12:23:45Z","timestamp":1750249425000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1749603.1749604"}},"subtitle":["A survey"],"short-title":[],"issued":{"date-parts":[[2010,6]]},"references-count":216,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2010,6]]}},"alternative-id":["10.1145\/1749603.1749604"],"URL":"https:\/\/doi.org\/10.1145\/1749603.1749604","relation":{},"ISSN":["0360-0300","1557-7341"],"issn-type":[{"type":"print","value":"0360-0300"},{"type":"electronic","value":"1557-7341"}],"subject":[],"published":{"date-parts":[[2010,6]]},"assertion":[{"value":"2004-11-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2008-12-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2010-06-23","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}