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Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2015,1,23]]},"abstract":"<jats:p>\n            This article presents a reconfigurable hardware\/software architecture for binary acceleration of embedded applications. A Reconfigurable Processing Unit (RPU) is used as a coprocessor of the General Purpose Processor (GPP) to accelerate the execution of repetitive instruction sequences called\n            <jats:italic>Megablocks<\/jats:italic>\n            . A toolchain detects Megablocks from instruction traces and generates customized RPU implementations. The implementation of Megablocks with memory accesses uses a memory-sharing mechanism to support concurrent accesses to the entire address space of the GPP\u2019s data memory. The scheduling of load\/store operations and memory access handling have been optimized to minimize the latency introduced by memory accesses. The system is able to dynamically switch the execution between the GPP and the RPU when executing the original binaries of the input application. Our proof-of-concept prototype achieved geometric mean speedups of 1.60\u00d7 and 1.18\u00d7 for, respectively, a set of 37 benchmarks and a subset considering the 9 most complex benchmarks. With respect to a previous version of our approach, we achieved geometric mean speedup improvements from 1.22 to 1.53 for the 10 benchmarks previously used.\n          <\/jats:p>","DOI":"10.1145\/2629468","type":"journal-article","created":{"date-parts":[[2015,1,5]],"date-time":"2015-01-05T13:27:09Z","timestamp":1420464429000},"page":"1-20","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses"],"prefix":"10.1145","volume":"7","author":[{"given":"Nuno","family":"Paulino","sequence":"first","affiliation":[{"name":"INESC TEC and Faculty of Engineering, University of Porto, Portugal"}]},{"given":"Jo\u00e3o Canas","family":"Ferreira","sequence":"additional","affiliation":[{"name":"INESC TEC and Faculty of Engineering, University of Porto, Portugal"}]},{"given":"Jo\u00e3o M. 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In Proceedings of the International Conference on Field-Programmable Technology (FPT\u201910). 437--440."},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2010.61"},{"key":"e_1_2_1_5_1","volume-title":"Ferreira","author":"Bispo Jo\u00e3o","year":"2013","unstructured":"Jo\u00e3o Bispo , Nuno Paulino , Jo\u00e3o M. P. Cardoso , and Jo\u00e3o C . Ferreira . 2013 a. Transparent runtime migration of loop-based traces of processor instructions to reconfigurable processing units. International Journal of Reconfigurable Computing (2013), 20. Article ID 340316. Jo\u00e3o Bispo, Nuno Paulino, Jo\u00e3o M. P. Cardoso, and Jo\u00e3o C. Ferreira. 2013a. Transparent runtime migration of loop-based traces of processor instructions to reconfigurable processing units. International Journal of Reconfigurable Computing (2013), 20. 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Designing the Low-Power M&ast;CORE Architecture . In Proceedings of the Power Driven Microarchitecture Workshop at the IEEE International Symposium on Circuits and Systems (ISCAS\u201998) . Barcelona, Spain. Jeff Scott, Lea Hwang Lee, John Arends, and Bill Moyer. 1998. Designing the Low-Power M&ast;CORE Architecture. In Proceedings of the Power Driven Microarchitecture Workshop at the IEEE International Symposium on Circuits and Systems (ISCAS\u201998). Barcelona, Spain."},{"key":"e_1_2_1_17_1","unstructured":"Seoul National University. 2006. SNU Real-Time Benchmarks. Retrieved from http:\/\/www.cprover.org\/goto-cc\/examples\/snu.html.  Seoul National University. 2006. SNU Real-Time Benchmarks. Retrieved from http:\/\/www.cprover.org\/goto-cc\/examples\/snu.html."},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1970353.1970365"},{"key":"e_1_2_1_19_1","unstructured":"Texas Instruments. 2008. TMS320C6000 Image Library (IMGLIB) - SPRC264. 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