{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,24]],"date-time":"2026-02-24T16:08:54Z","timestamp":1771949334947,"version":"3.50.1"},"reference-count":25,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2015,2,17]],"date-time":"2015-02-17T00:00:00Z","timestamp":1424131200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"Portuguese Funda&ccedil;&atilde;o para a Ci&ecirc;ncia e Tecnologia (FCT) under the FCT projects PEst-OE\/EEI\/LA0008\/2013, UID\/EEA\/50008\/2013","award":["SFRH\/BD\/78238\/2011"],"award-info":[{"award-number":["SFRH\/BD\/78238\/2011"]}]},{"name":"EC Marie Curie International Reintegration Grant (IRG) 223819"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2015,3,25]]},"abstract":"<jats:p>The design cycle for complex special-purpose computing systems is extremely costly and time-consuming. It involves a multiparametric design space exploration for optimization, followed by design verification. Designers of special purpose VLSI implementations often need to explore parameters, such as optimal bitwidth and data representation, through time-consuming Monte Carlo simulations. A prominent example of this simulation-based exploration process is the design of decoders for error correcting systems, such as the Low-Density Parity-Check (LDPC) codes adopted by modern communication standards, which involves thousands of Monte Carlo runs for each design point. Currently, high-performance computing offers a wide set of acceleration options that range from multicore CPUs to Graphics Processing Units (GPUs) and Field Programmable Gate Arrays (FPGAs). The exploitation of diverse target architectures is typically associated with developing multiple code versions, often using distinct programming paradigms. In this context, we evaluate the concept of retargeting a single OpenCL program to multiple platforms, thereby significantly reducing design time. A single OpenCL-based parallel kernel is used without modifications or code tuning on multicore CPUs, GPUs, and FPGAs. We use SOpenCL (Silicon to OpenCL), a tool that automatically converts OpenCL kernels to RTL in order to introduce FPGAs as a potential platform to efficiently execute simulations coded in OpenCL. We use LDPC decoding simulations as a case study. Experimental results were obtained by testing a variety of regular and irregular LDPC codes that range from short\/medium (e.g., 8,000 bit) to long length (e.g., 64,800 bit) DVB-S2 codes. We observe that, depending on the design parameters to be simulated, on the dimension and phase of the design, the GPU or FPGA may suit different purposes more conveniently, thus providing different acceleration factors over conventional multicore CPUs.<\/jats:p>","DOI":"10.1145\/2656207","type":"journal-article","created":{"date-parts":[[2015,3,3]],"date-time":"2015-03-03T14:08:19Z","timestamp":1425391699000},"page":"1-23","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":11,"title":["Enhancing Design Space Exploration by Extending CPU\/GPU Specifications onto FPGAs"],"prefix":"10.1145","volume":"14","author":[{"given":"Muhsen","family":"Owaida","sequence":"first","affiliation":[{"name":"University of Thessaly, Lausanne, Switzerland"}]},{"given":"Gabriel","family":"Falcao","sequence":"additional","affiliation":[{"name":"University of Coimbra, Coimbra, Portugal"}]},{"given":"Joao","family":"Andrade","sequence":"additional","affiliation":[{"name":"University of Coimbra, Coimbra, Portugal"}]},{"given":"Christos","family":"Antonopoulos","sequence":"additional","affiliation":[{"name":"University of Thessaly, Greece"}]},{"given":"Nikolaos","family":"Bellas","sequence":"additional","affiliation":[{"name":"University of Thessaly, Greece"}]},{"given":"Madhura","family":"Purnaprajna","sequence":"additional","affiliation":[{"name":"EPFL, Lausanne, Switzerland"}]},{"given":"David","family":"Novo","sequence":"additional","affiliation":[{"name":"EPFL, Lausanne, Switzerland"}]},{"given":"Georgios","family":"Karakonstantis","sequence":"additional","affiliation":[{"name":"EPFL, United Kingdom"}]},{"given":"Andreas","family":"Burg","sequence":"additional","affiliation":[{"name":"EPFL, Lausanne, Switzerland"}]},{"given":"Paolo","family":"Ienne","sequence":"additional","affiliation":[{"name":"EPFL, Lausanne, Switzerland"}]}],"member":"320","published-online":{"date-parts":[[2015,2,17]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1950413.1950423"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2009.179"},{"key":"e_1_2_1_3_1","volume-title":"European Telecommunications Standards Institute (ETSI)","author":"EN","year":"2005","unstructured":"EN 302 307 V1. 1.1 , European Telecommunications Standards Institute (ETSI) . 2005 . Digital video broadcasting (DVB) ; second generation framing structure, channel coding and modulation systems for broadcasting, interactive services, news gathering and other broad-band satellite applications. (2005). EN 302 307 V1. 1.1, European Telecommunications Standards Institute (ETSI). 2005. Digital video broadcasting (DVB); second generation framing structure, channel coding and modulation systems for broadcasting, interactive services, news gathering and other broad-band satellite applications. (2005)."},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1002\/sat.787"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1049\/el.2011.0201"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/MSP.2012.2192212"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.1962.1057683"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2011.31"},{"key":"e_1_2_1_9_1","volume-title":"Proceedings of the 2nd International Symposium on Turbo Codes &amp; Related Topics.","author":"Jin H.","unstructured":"H. Jin , A. Khandekar , and R. McEliece . 2000. Irregular repeat-accumulate codes . In Proceedings of the 2nd International Symposium on Turbo Codes &amp; Related Topics. H. Jin, A. Khandekar, and R. McEliece. 2000. Irregular repeat-accumulate codes. In Proceedings of the 2nd International Symposium on Turbo Codes &amp; Related Topics."},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2002.1033026"},{"key":"e_1_2_1_11_1","unstructured":"Group Khronos. 2010. OpenCL -- The Open Standard for Parallel Programming of Heterogeneous Systems. Retrieved from http:\/\/www.khronos.org\/opencl.  Group Khronos. 2010. OpenCL -- The Open Standard for Parallel Programming of Heterogeneous Systems. Retrieved from http:\/\/www.khronos.org\/opencl."},{"key":"e_1_2_1_12_1","volume-title":"Proceedings of the International Symposium on Code Generation and Optimization (CGO'04)","author":"Lattner C.","unstructured":"C. Lattner and V. Adve . 2004. LLVM: A compilation framework for lifelong program analysis transformation . In Proceedings of the International Symposium on Code Generation and Optimization (CGO'04) . 75--86. C. Lattner and V. Adve. 2004. LLVM: A compilation framework for lifelong program analysis transformation. In Proceedings of the International Symposium on Code Generation and Optimization (CGO'04). 75--86."},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2010.93"},{"key":"e_1_2_1_14_1","volume-title":"Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT'96)","author":"Llosa J.","unstructured":"J. Llosa , A. Gonzalez , E. Ayguade , and M. Valero . 1996. Swing modulo scheduling: A lifetime-sensitive approach . In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT'96) . 80--90. J. Llosa, A. Gonzalez, E. Ayguade, and M. Valero. 1996. Swing modulo scheduling: A lifetime-sensitive approach. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT'96). 80--90."},{"key":"e_1_2_1_15_1","unstructured":"NVIDIA. 2007. CUDA -- Compute Unified Device Architecture. Retrieved from http:\/\/www.nvidia.com\/object\/cuda_home_new.html.  NVIDIA. 2007. CUDA -- Compute Unified Device Architecture. Retrieved from http:\/\/www.nvidia.com\/object\/cuda_home_new.html."},{"key":"e_1_2_1_17_1","volume-title":"Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design (ICCAD).","author":"Owaida M.","unstructured":"M. Owaida , N. Bellas , K. Daloukas , and C. D. Antonopoulos . 2011a. Massively parallel programming models used as hardware description language: The OpenCL case . In Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design (ICCAD). M. Owaida, N. Bellas, K. Daloukas, and C. D. Antonopoulos. 2011a. Massively parallel programming models used as hardware description language: The OpenCL case. In Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)."},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2011.19"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/SASP.2009.5226333"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1016\/S0165-1684(03)00090-2"},{"key":"e_1_2_1_21_1","first-page":"1","article-title":"Staircase codes: FEC for 100 Gb\/s OTN","volume":"99","author":"Smith B.","year":"2011","unstructured":"B. Smith , A. Farhood , A. Hunt , F. Kschischang , and J. Lodge . 2011 . Staircase codes: FEC for 100 Gb\/s OTN . IEEE\/OSA Lightwave Technology PP , 99 (2011), 1 . B. Smith, A. Farhood, A. Hunt, F. Kschischang, and J. Lodge. 2011. Staircase codes: FEC for 100 Gb\/s OTN. IEEE\/OSA Lightwave Technology PP, 99 (2011), 1.","journal-title":"IEEE\/OSA Lightwave Technology PP"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/349299.349317"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2010.125"},{"key":"e_1_2_1_24_1","unstructured":"S. B. Wicker and S. Kim. 2003. Fundamentals of Codes Graphs and Iterative Decoding. Kluwer Academic Publishers.   S. B. Wicker and S. Kim. 2003. Fundamentals of Codes Graphs and Iterative Decoding. Kluwer Academic Publishers."},{"key":"e_1_2_1_25_1","volume-title":"Proceedings of the International Symposium on Circuits and Systems (ISCAS'12)","author":"Yu Chi-Li","year":"2012","unstructured":"Chi-Li Yu and C. Chakrabarti . 2012. Transpose-free sar imaging on fpga platform . In Proceedings of the International Symposium on Circuits and Systems (ISCAS'12) . 762--765. DOI:http:\/\/dx.doi.org\/10.1109\/ISCAS. 2012 .6272149 10.1109\/ISCAS.2012.6272149 Chi-Li Yu and C. Chakrabarti. 2012. Transpose-free sar imaging on fpga platform. In Proceedings of the International Symposium on Circuits and Systems (ISCAS'12). 762--765. DOI:http:\/\/dx.doi.org\/10.1109\/ISCAS.2012.6272149"},{"key":"e_1_2_1_26_1","unstructured":"Z. Zhang Y. Fan W. Jiang G. Han C. Yang and J. Cong. 2008. High-Level Synthesis: From Algorithm to Digital Circuit. Springer Netherlands Chapter AutoPilot: A Platform-Based ESL Synthesis System.   Z. Zhang Y. Fan W. Jiang G. Han C. Yang and J. Cong. 2008. High-Level Synthesis: From Algorithm to Digital Circuit. Springer Netherlands Chapter AutoPilot: A Platform-Based ESL Synthesis System."}],"container-title":["ACM Transactions on Embedded Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2656207","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2656207","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T07:19:37Z","timestamp":1750231177000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2656207"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,2,17]]},"references-count":25,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2015,3,25]]}},"alternative-id":["10.1145\/2656207"],"URL":"https:\/\/doi.org\/10.1145\/2656207","relation":{},"ISSN":["1539-9087","1558-3465"],"issn-type":[{"value":"1539-9087","type":"print"},{"value":"1558-3465","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,2,17]]},"assertion":[{"value":"2013-04-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2014-09-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2015-02-17","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}