{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,17]],"date-time":"2025-09-17T16:24:38Z","timestamp":1758126278158},"reference-count":10,"publisher":"IBM","issue":"1.2","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IBM J. Res. &amp; Dev."],"published-print":{"date-parts":[[2012,1]]},"DOI":"10.1147\/jrd.2011.2177106","type":"journal-article","created":{"date-parts":[[2012,2,2]],"date-time":"2012-02-02T15:11:38Z","timestamp":1328195498000},"page":"4:1-4:11","source":"Crossref","is-referenced-by-count":30,"title":["IBM zEnterprise redundant array of independent memory subsystem"],"prefix":"10.1147","volume":"56","author":[{"given":"P. J.","family":"Meaney","sequence":"first","affiliation":[]},{"given":"L. A.","family":"Lastras-Montano","sequence":"additional","affiliation":[]},{"given":"V. K.","family":"Papazova","sequence":"additional","affiliation":[]},{"given":"E.","family":"Stephens","sequence":"additional","affiliation":[]},{"given":"J. S.","family":"Johnson","sequence":"additional","affiliation":[]},{"given":"L. C.","family":"Alves","sequence":"additional","affiliation":[]},{"given":"J. A.","family":"O'Connor","sequence":"additional","affiliation":[]},{"given":"W. J.","family":"Clarke","sequence":"additional","affiliation":[]}],"member":"3082","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2004.5388891"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1137\/0108018"},{"key":"ref10","first-page":"1","article-title":"A new class of array codes for memory storage","author":"lastras-monta\u00f1o","year":"2011","journal-title":"Proc Inf Theory Appl Workshop"},{"key":"ref6","article-title":"The Intel&#x00AE; Itanium&#x00AE; Processor 9300 Series: A Technical Overview for IT Decision-Makers","author":"agny","year":"2010","journal-title":"White Paper"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/50202.50214"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2011.2173962"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/FTCS.1994.315616"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"124","DOI":"10.1147\/rd.282.0124","article-title":"Error-correcting codes for semiconductor memory applications: A state-of-the-art review","volume":"28","author":"hsiao","year":"1984","journal-title":"IBM J Res & Dev"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2011.2177897"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2011.34"}],"container-title":["IBM Journal of Research and Development"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5288520\/6136228\/06136239.pdf?arnumber=6136239","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,11,14]],"date-time":"2017-11-14T08:05:21Z","timestamp":1510646721000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6136239\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,1]]},"references-count":10,"journal-issue":{"issue":"1.2"},"URL":"https:\/\/doi.org\/10.1147\/jrd.2011.2177106","relation":{},"ISSN":["0018-8646","0018-8646"],"issn-type":[{"value":"0018-8646","type":"print"},{"value":"0018-8646","type":"electronic"}],"subject":[],"published":{"date-parts":[[2012,1]]}}}