{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,23]],"date-time":"2025-10-23T18:03:26Z","timestamp":1761242606774,"version":"build-2065373602"},"reference-count":10,"publisher":"IBM","issue":"4\/5","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IBM J. Res. & Dev."],"published-print":{"date-parts":[[2015,7]]},"DOI":"10.1147\/jrd.2015.2429031","type":"journal-article","created":{"date-parts":[[2015,8,3]],"date-time":"2015-08-03T14:23:29Z","timestamp":1438611809000},"page":"4:1-4:11","source":"Crossref","is-referenced-by-count":17,"title":["The IBM z13 memory subsystem for big data"],"prefix":"10.1147","volume":"59","author":[{"given":"P. J.","family":"Meaney","sequence":"first","affiliation":[]},{"given":"L. D.","family":"Curley","sequence":"additional","affiliation":[]},{"given":"G. D.","family":"Gilda","sequence":"additional","affiliation":[]},{"given":"M. R.","family":"Hodges","sequence":"additional","affiliation":[]},{"given":"D. J.","family":"Buerkle","sequence":"additional","affiliation":[]},{"given":"R. D.","family":"Siegl","sequence":"additional","affiliation":[]},{"given":"R. K.","family":"Dong","sequence":"additional","affiliation":[]}],"member":"3082","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2011.2177897"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2015.2428591"},{"year":"1992","key":"ref10","article-title":"IBM ESA\/390 principles of operation"},{"key":"ref6","first-page":"1","article-title":"A new class of array codes for memory storage","author":"lastras-montano","year":"2011","journal-title":"Proc Inf Theory Appl Workshop"},{"key":"ref5","first-page":"9","article-title":"Next generation POWER microprocessor","author":"stuecheli","year":"0","journal-title":"Proc HOT Chip Symp"},{"key":"ref8","first-page":"178","article-title":"POWER7 local clocking and clocked storage elements","author":"warnock","year":"2010","journal-title":"Proc IEEE ISSCC Dig Tech Papers"},{"key":"ref7","first-page":"70","article-title":"A 5.2 GHz microprocessor chip for the IBM zEnterprise system","author":"warnock","year":"2011","journal-title":"Proc IEEE ISSCC Dig Tech Papers"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2011.2177106"},{"year":"2012","key":"ref9","first-page":"81"},{"key":"ref1","first-page":"22","article-title":"IBM zEC12 processor subsystem","author":"sonnelitter","year":"2014"}],"container-title":["IBM Journal of Research and Development"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/5288520\/7175088\/07175139.pdf?arnumber=7175139","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,10,23]],"date-time":"2025-10-23T17:57:34Z","timestamp":1761242254000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/7175139\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,7]]},"references-count":10,"journal-issue":{"issue":"4\/5"},"URL":"https:\/\/doi.org\/10.1147\/jrd.2015.2429031","relation":{},"ISSN":["0018-8646","0018-8646"],"issn-type":[{"type":"print","value":"0018-8646"},{"type":"electronic","value":"0018-8646"}],"subject":[],"published":{"date-parts":[[2015,7]]}}}