{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,22]],"date-time":"2026-01-22T07:17:50Z","timestamp":1769066270895,"version":"3.49.0"},"reference-count":29,"publisher":"IBM","issue":"4\/5","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IBM J. Res. &amp; Dev."],"published-print":{"date-parts":[[2017,7,1]]},"DOI":"10.1147\/jrd.2017.2716579","type":"journal-article","created":{"date-parts":[[2017,9,8]],"date-time":"2017-09-08T14:20:05Z","timestamp":1504880405000},"page":"11:1-11:11","source":"Crossref","is-referenced-by-count":56,"title":["Toward on-chip acceleration of the backpropagation algorithm using nonvolatile memory"],"prefix":"10.1147","volume":"61","author":[{"given":"P.","family":"Narayanan","sequence":"first","affiliation":[]},{"given":"A.","family":"Fumarola","sequence":"additional","affiliation":[]},{"given":"L. L.","family":"Sanches","sequence":"additional","affiliation":[]},{"given":"K.","family":"Hosokawa","sequence":"additional","affiliation":[]},{"given":"S. C.","family":"Lewis","sequence":"additional","affiliation":[]},{"given":"R. M.","family":"Shelby","sequence":"additional","affiliation":[]},{"given":"G. W.","family":"Burr","sequence":"additional","affiliation":[]}],"member":"3082","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1049\/el:19910489"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/IJCNN.2014.6889893"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1038\/nature14441"},{"key":"ref13","first-page":"267","article-title":"Minerva: Enabling low-power, highly-accurate deep neural network accelerators","author":"reagen","year":"0","journal-title":"Proc 43rd Annu Int Symp Comput Archit"},{"key":"ref14","first-page":"27","article-title":"PRIME: A novel processing-in-memory architecture for neural network computation in ReRAM-based main memory","volume":"43","author":"chi","year":"2016","journal-title":"Proc 43rd Annu Int Symp Comput Archit"},{"key":"ref15","first-page":"14","article-title":"ISAAC: A convolutional neural network accelerator with in-situ analog arithmetic in crossbars","author":"shafiee","year":"0","journal-title":"Proc 43rd Annu Int Symp Comput Archit"},{"key":"ref16","first-page":"17.3.1","article-title":"Scaling-up resistive synaptic arrays for neuro-inspired architecture: Challenges and prospect","author":"yu","year":"0","journal-title":"Proc IEEE Int Electron Devices Meet"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1088\/0957-4484\/26\/45\/455204"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1016\/j.neucom.2016.10.061"},{"key":"ref19","first-page":"118","article-title":"Neuromorphic architectures with electronic synapses","author":"eryilmaz","year":"0","journal-title":"Proc 17th Int Symp Qual Electron Des"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2015.7372570"},{"key":"ref4","first-page":"4.4.1","article-title":"Large&#x2013;scale neural networks implemented with nonvolatile memory as the synaptic weight element: comparative performance analysis (accuracy, speed, and power)","author":"burr","year":"0","journal-title":"Proc Int Electron Devices Meeting"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/5.726791"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2015.2439635"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ESSDERC.2016.7599680"},{"key":"ref29","article-title":"TensorFlow: Large-scale machine learning on heterogeneous distributed systems","author":"abadi","year":"2016"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2015.2418342"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2017.8050988"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICRC.2016.7738684"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2014.7047135"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/72.129421"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1126\/science.1254642"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.3389\/fnins.2016.00333"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.3389\/fnins.2011.00073"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TNNLS.2014.2383395"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2016.2598413"},{"key":"ref23","first-page":"17.1.1","article-title":"NVM neuromorphic core with 64k-cell (256-by-256) phase change memory synaptic array with on-chip neuron circuits for continuous in-situ learning","author":"kim","year":"2015","journal-title":"Proc IEEE Int Electron Devices Meeting"},{"key":"ref26","doi-asserted-by":"crossref","DOI":"10.7551\/mitpress\/5236.003.0018","article-title":"A general framework for parallel distributed processing","author":"rumelhart","year":"1986","journal-title":"Parallel Distributed Processing"},{"key":"ref25","doi-asserted-by":"crossref","DOI":"10.1116\/1.4889999","article-title":"Access devices for 3D crosspoint memory","volume":"32","author":"burr","year":"2014","journal-title":"J Vacuum Sci Technol B"}],"container-title":["IBM Journal of Research and Development"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/5288520\/8030196\/08030206.pdf?arnumber=8030206","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,10,20]],"date-time":"2025-10-20T17:55:22Z","timestamp":1760982922000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8030206\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,7,1]]},"references-count":29,"journal-issue":{"issue":"4\/5"},"URL":"https:\/\/doi.org\/10.1147\/jrd.2017.2716579","relation":{},"ISSN":["0018-8646","0018-8646"],"issn-type":[{"value":"0018-8646","type":"print"},{"value":"0018-8646","type":"electronic"}],"subject":[],"published":{"date-parts":[[2017,7,1]]}}}