{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,20]],"date-time":"2026-03-20T20:25:12Z","timestamp":1774038312238,"version":"3.50.1"},"reference-count":50,"publisher":"IBM","issue":"4\/5","funder":[{"DOI":"10.13039\/100004316","name":"IBM Research","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100004316","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000185","name":"Defense Advanced Research Projects Agency","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100000185","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100021681","name":"Microsystems Technology Office","doi-asserted-by":"crossref","award":["HR0011-13-C-0022"],"award-info":[{"award-number":["HR0011-13-C-0022"]}],"id":[{"id":"10.13039\/100021681","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/100000005","name":"Department of Defense","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100000005","id-type":"DOI","asserted-by":"publisher"}]},{"name":"U.S. Government"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IBM J. Res. & Dev."],"published-print":{"date-parts":[[2017,7,1]]},"DOI":"10.1147\/jrd.2017.2721699","type":"journal-article","created":{"date-parts":[[2017,9,13]],"date-time":"2017-09-13T14:07:55Z","timestamp":1505311675000},"page":"13:1-13:14","source":"Crossref","is-referenced-by-count":11,"title":["Machine learning techniques for taming the complexity of modern hardware design"],"prefix":"10.1147","volume":"61","author":[{"given":"M. M.","family":"Ziegler","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"R.","family":"Bertran","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"Buyuktosunoglu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"P.","family":"Bose","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"3082","reference":[{"key":"ref39","first-page":"342","article-title":"Latchplanner: Latch placement algorithm for datapath-oriented high-performance VLSI designs","year":"0","journal-title":"Proc Int Conf Comput -Aided Des"},{"key":"ref38","first-page":"139","article-title":"Network flow based datapath bit slicing","year":"0","journal-title":"Proc ACM Int Symp Phys Des"},{"key":"ref33","first-page":"286","article-title":"Machine learning and pattern matching in physical design","year":"0","journal-title":"Proc Asia South Pac Des Autom Conf"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/2076450.2076469"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2014.2363392"},{"key":"ref30","article-title":"On learning-based methods for design-space exploration with high-level synthesis","year":"0","journal-title":"Proc Des Autom Conf"},{"key":"ref37","first-page":"756","article-title":"PADE: A high-performance placer with automatic datapath extraction and evaluation through high dimensional data learning","year":"0","journal-title":"Proc Des Autom Conf"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2593902"},{"key":"ref35","first-page":"491","article-title":"Machine learning-based anomaly detection for post-silicon bug diagnosis","year":"0","journal-title":"Proc Des Autom Test Eur Conf Exhib"},{"key":"ref34","year":"0"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2011.41"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2010.95"},{"key":"ref29","first-page":"599","article-title":"Clock power minimization using structured latch templates and decision tree induction","year":"0","journal-title":"Proc Int Conf Comput -Aided Des"},{"key":"ref2","article-title":"22nm next-generation IBM system z microprocessor","year":"0","journal-title":"Proc IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref1","first-page":"125","article-title":"The impact of AI technology on VLSI design","year":"0","journal-title":"Proc AFIPS Natl Comp Conf"},{"key":"ref20","doi-asserted-by":"crossref","first-page":"113","DOI":"10.1147\/rd.391.0113","article-title":"Architectural timing verification of CMOS RISC processors","volume":"39","year":"1995","journal-title":"IBM J Res & Dev"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2004.1277900"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/92.386220"},{"key":"ref24","first-page":"3:1?3:11","article-title":"Functional verification of the IBM system z10 processor chipset","volume":"53","year":"2009","journal-title":"IBM J Res & Dev"},{"key":"ref23","first-page":"1720","article-title":"Constraint-based random stimuli generation for hardware verification","volume":"28","year":"2006","journal-title":"Amer Assoc Artif Intell AI Mag"},{"key":"ref26","first-page":"69","article-title":"Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events","year":"2006","journal-title":"Proc Des Autom Conf"},{"key":"ref25","first-page":"286","article-title":"Coverage directed test generation for functional verification using Bayesian networks","year":"2003","journal-title":"Proc Des Autom Conf"},{"key":"ref50","doi-asserted-by":"crossref","first-page":"668","DOI":"10.1126\/science.1254642","article-title":"A million spiking-neuron integrated circuit with a scalable communication network and interface","volume":"345","year":"2014","journal-title":"Science"},{"key":"ref10","first-page":"340","article-title":"Illustrative design space studies with microarchitectural regression models","year":"0","journal-title":"Proc 13th IEEE Int Symp High-Perform Comput Archit"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2015.2446871"},{"key":"ref40","first-page":"180","article-title":"Scalable auto-tuning of synthesis parameters for optimizing high-performance processors","year":"0","journal-title":"Proc Int Symp Low Power Electron Des"},{"key":"ref12","first-page":"1","article-title":"POWER8 design methodology innovations for improving productivity and reducing power","year":"0","journal-title":"Proc IEEE Custom Integr Circuits Conf"},{"key":"ref13","first-page":"543","article-title":"A new approach to logic synthesis","year":"0","journal-title":"Proc Des Autom Conf"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1147\/rd.285.0537"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2004.1261846"},{"key":"ref16","first-page":"1148","article-title":"A synthesis-parameter tuning system for autonomous design-space exploration","year":"0","journal-title":"Proc Des Autom Test Eur Conf Exhib"},{"key":"ref17","article-title":"Big data analytics in EDA","year":"2015","journal-title":"Proc Panel Discuss Des Autom Conf"},{"key":"ref18","first-page":"199","article-title":"Systematic energy characterization of CMP\/SMT processor systems via automated microbenchmarks","year":"0","journal-title":"Proc 45th Annu IEEE\/ACM Int Symp Microarchit"},{"key":"ref19","first-page":"16:1?16:12","article-title":"Robust power management in the IBM z13","volume":"59","year":"2015","journal-title":"IBM J Res & Dev"},{"key":"ref4","first-page":"166","article-title":"Unified methodology for resolving power-performance tradeoffs at the microarchitectural and circuit levels","year":"0","journal-title":"Proc Int Symp Low Power Electron Des"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1147\/rd.446.0851"},{"key":"ref6","year":"2006","journal-title":"The Pentium Chronicles The People Passion and Politics Behind Intel's Landmark Chips"},{"key":"ref5","first-page":"250","article-title":"An integrated framework for joint design space exploration of microarchitecture and circuits","year":"0","journal-title":"Proc Des Autom Test Eur Conf Exhib"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2014.2379634"},{"key":"ref7","first-page":"163","article-title":"Performance evaluation of the powerpc620 microarchitecture","year":"0","journal-title":"Proc Int Symp Comput Archit"},{"key":"ref49","article-title":"Google designing AI processors","year":"2015"},{"key":"ref9","first-page":"185","article-title":"Accurate and efficient regression modeling for microarchitectural performance and power prediction","year":"0","journal-title":"Proc Int Conf Archit Support Program Lang Oper Syst"},{"key":"ref46","first-page":"152","article-title":"Dissecting xeon+ FPGA: Why the integration of CPUs and FPGAs makes a power difference for the datacenter","year":"0","journal-title":"Proc Int Symp Low Power Electron Des"},{"key":"ref45","first-page":"13","article-title":"A reconfigurable fabric for accelerating large-scale datacenter services","year":"0","journal-title":"Proc Int Symp Comput Archit"},{"key":"ref48","first-page":"267","article-title":"Minerva: Enabling low-power, highly-accurate deep neural network accelerators","year":"0","journal-title":"Proc Int Symp Comput Archit"},{"key":"ref47","first-page":"99","article-title":"Towards general-purpose neural network computing","year":"0","journal-title":"Proc Int Conf Parallel Archit Compil"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2012.97"},{"key":"ref41","first-page":"421","article-title":"Power reduction by aggressive synthesis design space exploration","year":"0","journal-title":"Proc Int Symp Low Power Electron Des"},{"key":"ref44","first-page":"1115","article-title":"Using GPUs for machine learning algorithms","year":"0","journal-title":"Proc 8th Int Conf Document Anal Recognit"},{"key":"ref43","article-title":"Fathom: Reference workloads for modern deep learning methods","year":"0","journal-title":"Proc IEEE Int Symp Workload Characterization"}],"container-title":["IBM Journal of Research and Development"],"original-title":[],"link":[{"URL":"https:\/\/ieeexplore.ieee.org\/ielam\/5288520\/8030196\/8032559-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/5288520\/8030196\/08032559.pdf?arnumber=8032559","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T18:03:22Z","timestamp":1761588202000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8032559\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,7,1]]},"references-count":50,"journal-issue":{"issue":"4\/5"},"URL":"https:\/\/doi.org\/10.1147\/jrd.2017.2721699","relation":{},"ISSN":["0018-8646","0018-8646"],"issn-type":[{"value":"0018-8646","type":"print"},{"value":"0018-8646","type":"electronic"}],"subject":[],"published":{"date-parts":[[2017,7,1]]}}}